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authorPalmer Dabbelt2015-11-02 11:37:29 -0800
committerPalmer Dabbelt2015-11-02 13:30:10 -0800
commitc6bd684119f44422c7195b7c22a3d55f5389d10a (patch)
treecec25c8dad59a5db45275593e2957c83fc9a810c /src
parent29e97f0bb4997f57378aa840af14f36132aedc9f (diff)
Remove "generates {,no} logic" comments
At least one of these is incorrect.
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Chisel/Aggregate.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index c17644b4..3d419934 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -128,7 +128,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
def := (that: Vec[T]): Unit = this connect that
/** Creates a dynamically indexed read or write accessor into the array.
- * Generates logic (likely some kind of multiplexer).
*/
def apply(idx: UInt): T = {
val x = gen
@@ -137,7 +136,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
}
/** Creates a statically indexed read or write accessor into the array.
- * Generates no logic.
*/
def apply(idx: Int): T = self(idx)