Merge pull request #95 from ucb-bar/flipped

Add Flipped trait; fix DeqIO, this fix looks good to go

3 files changed, 75 insertions, 12 deletions

diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index 0ac3ee32..2ae9ec63 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -19,6 +19,11 @@ object debug {  // scalastyle:ignore object.name
   def apply (arg: Data): Data = arg
 }
 
+/** Mixing in this trait flips the direction of an Aggregate. */
+trait Flipped extends Data {
+  this.overrideDirection(_.flip, !_)
+}
+
 /** This forms the root of the type system for wire data types. The data value
   * must be representable as some number (need not be known at Chisel compile
   * time) of bits, and must have methods to pack / unpack structured data to /
@@ -32,17 +37,16 @@ abstract class Data(dirArg: Direction) extends HasId {
   private var dirVar = dirArg
   private[Chisel] def isFlip = isFlipVar
 
-  private def cloneWithDirection(newDir: Direction => Direction,
-                                 newFlip: Boolean => Boolean): this.type = {
-    val res = this.cloneType
-    res.isFlipVar = newFlip(res.isFlipVar)
-    for ((me, it) <- this.flatten zip res.flatten)
-      (it: Data).dirVar = newDir((me: Data).dirVar)
-    res
+  private[Chisel] def overrideDirection(newDir: Direction => Direction,
+                                        newFlip: Boolean => Boolean): this.type = {
+    this.isFlipVar = newFlip(this.isFlipVar)
+    for (field <- this.flatten)
+      (field: Data).dirVar = newDir((field: Data).dirVar)
+    this
   }
-  def asInput: this.type = cloneWithDirection(_ => INPUT, _ => true)
-  def asOutput: this.type = cloneWithDirection(_ => OUTPUT, _ => false)
-  def flip(): this.type = cloneWithDirection(_.flip, !_)
+  def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true)
+  def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
+  def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
 
   private[Chisel] def badConnect(that: Data): Unit =
     throwException(s"cannot connect ${this} and ${that}")
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala
index ca000af9..23a08d52 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/Chisel/util/Decoupled.scala
@@ -33,9 +33,8 @@ class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
 }
 
 /** An I/O bundle for dequeuing data with valid/ready handshaking */
-class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen)
+class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
 {
-  flip()
   ready := Bool(false)
   def deq(b: Boolean = false): T = { ready := Bool(true); bits }
   override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
new file mode 100644
index 00000000..8f7937ab
--- /dev/null
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -0,0 +1,60 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import Chisel._
+import Chisel.testers.BasicTester
+
+/**
+  * Created by chick on 2/8/16.
+  */
+class UsesDeqIOInfo extends Bundle {
+  val test_width = 32
+
+  val info_data = UInt(width = test_width)
+}
+
+class UsesDeqIO extends Module {
+  val io = new Bundle {
+    val in = new DeqIO(new UsesDeqIOInfo)
+    val out = new EnqIO(new UsesDeqIOInfo)
+  }
+}
+
+class DeqIOSpec extends ChiselFlatSpec {
+  runTester {
+    new BasicTester {
+      val dut = new UsesDeqIO
+
+      "DeqIO" should "set the direction of it's parameter to INPUT" in {
+        assert(dut.io.in.bits.info_data.dir === INPUT)
+      }
+      "DeqIO" should "create a valid input and ready output" in {
+        assert(dut.io.in.valid.dir === INPUT)
+        assert(dut.io.in.ready.dir === OUTPUT)
+      }
+      "EnqIO" should "set the  direction of it's parameter OUTPUT" in {
+        assert(dut.io.out.bits.info_data.dir === OUTPUT)
+      }
+      "EnqIO" should "create a valid input and ready output" in {
+        assert(dut.io.out.valid.dir === OUTPUT)
+        assert(dut.io.out.ready.dir === INPUT)
+      }
+
+      val in_clone = dut.io.in.cloneType
+      val out_clone = dut.io.out.cloneType
+
+      "A deqIO device" should "clone itself with it's directions intact" in {
+        assert(dut.io.in.bits.info_data.dir == in_clone.bits.info_data.dir)
+        assert(dut.io.in.ready.dir == in_clone.ready.dir)
+        assert(dut.io.in.valid.dir == in_clone.valid.dir)
+      }
+
+      "A enqIO device" should "clone itself with it's directions intact" in {
+        assert(dut.io.out.bits.info_data.dir == out_clone.bits.info_data.dir)
+        assert(dut.io.out.ready.dir == out_clone.ready.dir)
+        assert(dut.io.out.valid.dir == out_clone.valid.dir)
+      }
+    }
+  }
+}