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authorducky2016-11-17 13:22:31 -0800
committerducky2016-11-21 13:31:12 -0800
commitc270598ddb8cbfa32f8c86cc5187c89d00e6ded0 (patch)
tree76567ca12ea4ed42732f96527e2b1ffae571488a /src
parent37a569372c70a651c813d0beb44124878a596e73 (diff)
Remove () from as_Int
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/chiselTests/Risc.scala12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 744e3631..57586c97 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -27,13 +27,13 @@ class Risc extends Module {
val rai = inst(15, 8)
val rbi = inst( 7, 0)
- val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
- val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
+ val ra = Mux(rai === 0.U, 0.U, file(rai))
+ val rb = Mux(rbi === 0.U, 0.U, file(rbi))
val rc = Wire(Bits(32.W))
io.valid := false.B
- io.out := 0.asUInt()
- rc := 0.asUInt()
+ io.out := 0.U
+ rc := 0.U
when (io.isWr) {
code(io.wrAddr) := io.wrData
@@ -45,12 +45,12 @@ class Risc extends Module {
is(imm_op) { rc := (rai << 8) | rbi }
}
io.out := rc
- when (rci === 255.asUInt()) {
+ when (rci === 255.U) {
io.valid := true.B
} .otherwise {
file(rci) := rc
}
- pc := pc +% 1.asUInt()
+ pc := pc +% 1.U
}
}