summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorducky2015-10-30 15:01:33 -0700
committerducky2015-10-30 15:01:33 -0700
commitb43551f807cd4a826862366aa6c184189a3b731e (patch)
tree64f7abc91f9adfbe67ba5ec00f85aa263f6e4c99 /src
parent22127c79c872ebcf5da50858c7309ad82d39eb63 (diff)
Fix whitespace
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Chisel/Bits.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 209dbd1f..695764d7 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -42,7 +42,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
/** Returns the specified bit on this wire as a [[Bool]], statically
* addressed. Generates no logic.
- *
+ *
* @note convenience method allowing direct use of Ints without implicits
*/
final def apply(x: Int): Bool =
@@ -149,9 +149,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
* 3 and value 7 (0b111) would become a SInt with value -1
*/
def asSInt(): SInt
-
+
/** Reinterpret cast to an UInt.
- *
+ *
* @note value not guaranteed to be preserved: for example, a SInt of width
* 3 and value -1 (0b111) would become an UInt with value 7
*/
@@ -159,7 +159,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
/** Reinterpret cast to Bits. */
def asBits(): Bits = asUInt
-
+
@deprecated("Use asSInt, which makes the reinterpret cast more explicit", "chisel3")
final def toSInt(): SInt = asSInt
@deprecated("Use asUInt, which makes the reinterpret cast more explicit", "chisel3")