Shift register enable gates all stages, not just first

Also, remove no-longer-special case for n=1.

1 files changed, 2 insertions, 4 deletions

diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 713a3b2e..f41d789c 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -55,10 +55,8 @@ object ShiftRegister
     */
   def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
     // The order of tests reflects the expected use cases.
-    if (n == 1) {
-      RegEnable(in, en)
-    } else if (n != 0) {
-      RegNext(apply(in, n-1, en))
+    if (n != 0) {
+      RegEnable(apply(in, n-1, en), en)
     } else {
       in
     }