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authorJim Lawson2016-10-06 09:40:07 -0700
committerGitHub2016-10-06 09:40:07 -0700
commita37973e0ed6150fc94d7e7a66640217e19b165a7 (patch)
tree4c29e334b8f57446ad6c7273ded7caeaab8c2763 /src
parent7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff)
parent2979cb900c4f6773210dbe174091c08e13e6c52a (diff)
Merge pull request #320 from ucb-bar/exitcode281
Update Driver: Check the simulation exit code #281
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/chisel3/Driver.scala9
-rw-r--r--src/test/scala/chiselTests/MultiAssign.scala5
2 files changed, 9 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 5e0a3a0f..190b36bf 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -86,14 +86,17 @@ trait BackendCompilationUtilities {
def executeExpectingFailure(
prefix: String,
dir: File,
- assertionMsg: String = "Assertion failed"): Boolean = {
+ assertionMsg: String = ""): Boolean = {
var triggered = false
+ val assertionMessageSupplied = assertionMsg != ""
val e = Process(s"./V${prefix}", dir) !
ProcessLogger(line => {
- triggered = triggered || line.contains(assertionMsg)
+ triggered = triggered || (assertionMessageSupplied && line.contains(assertionMsg))
System.out.println(line) // scalastyle:ignore regex
})
- triggered
+ // Fail if a line contained an assertion or if we get a non-zero exit code
+ // or, we get a SIGABRT (assertion failure) and we didn't provide a specific assertion message
+ triggered || (e != 0 && (e != 134 || !assertionMessageSupplied))
}
def executeExpectingSuccess(prefix: String, dir: File): Boolean = {
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fa4c4898..397ea4c2 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,7 +9,8 @@ import chisel3.testers.BasicTester
import chisel3.util._
class LastAssignTester() extends BasicTester {
- val cnt = Counter(2)
+ val countOnClockCycles = Bool(true)
+ val (cnt, wrap) = Counter(countOnClockCycles,2)
val test = Wire(UInt.width(4))
assert(test === 7.U) // allow read references before assign references
@@ -20,7 +21,7 @@ class LastAssignTester() extends BasicTester {
test := 7.U
assert(test === 7.U) // this obviously should work
- when(cnt.value === 1.U) {
+ when(cnt === 1.U) {
stop()
}
}