Add source info / compile options transforms to Mem accessors (#744)

Fixes #708

1 files changed, 26 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
new file mode 100644
index 00000000..81b5307c
--- /dev/null
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -0,0 +1,26 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.util._
+import chisel3.testers.BasicTester
+
+class MemVecTester extends BasicTester {
+  val mem = Mem(2, Vec(2, UInt(8.W)))
+
+  // Circuit style tester is definitely the wrong abstraction here
+  val (cnt, wrap) = Counter(true.B, 2)
+  mem(0)(0) := 1.U
+
+  when (cnt === 1.U) {
+    assert(mem.read(0.U)(0) === 1.U)
+    stop()
+  }
+}
+
+class MemorySpec extends ChiselPropSpec {
+  property("Mem of Vec should work") {
+    assertTesterPasses { new MemVecTester }
+  }
+}