From d67914ffd4b983903f777c5c033ce84fbdb561f1 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 19 Dec 2017 16:17:22 -0800
Subject: Add source info / compile options transforms to Mem accessors (#744)

Fixes #708---
 src/test/scala/chiselTests/Mem.scala | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 src/test/scala/chiselTests/Mem.scala

(limited to 'src')

diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
new file mode 100644
index 00000000..81b5307c
--- /dev/null
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -0,0 +1,26 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.util._
+import chisel3.testers.BasicTester
+
+class MemVecTester extends BasicTester {
+  val mem = Mem(2, Vec(2, UInt(8.W)))
+
+  // Circuit style tester is definitely the wrong abstraction here
+  val (cnt, wrap) = Counter(true.B, 2)
+  mem(0)(0) := 1.U
+
+  when (cnt === 1.U) {
+    assert(mem.read(0.U)(0) === 1.U)
+    stop()
+  }
+}
+
+class MemorySpec extends ChiselPropSpec {
+  property("Mem of Vec should work") {
+    assertTesterPasses { new MemVecTester }
+  }
+}
-- 
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