diff options
| author | Richard Lin | 2016-11-23 16:01:50 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-23 16:01:50 -0800 |
| commit | edb19a0559686a471141c74438f677c1e217a298 (patch) | |
| tree | 8745e2a31ab2e91f42c00999a68057916721bcdc /src/test | |
| parent | 08b4f68db403d6925fba8c9e943216ef8f38d69e (diff) | |
Simplify Enum API (#385)
Get rid of some cruft exposed in #373
This also allows Bits.fromtInt(...) to be removed. Yay!
All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.
The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/Risc.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/VendingMachine.scala | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 57586c97..0d03ff65 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -19,7 +19,7 @@ class Risc extends Module { val code = Mem(memSize, Bits(32.W)) val pc = Reg(init=0.U(8.W)) - val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2) + val add_op :: imm_op :: Nil = Enum(2) val inst = code(pc) val op = inst(31,24) diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index c474430b..712b5b7a 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -12,7 +12,7 @@ class VendingMachine extends Module { val valid = Output(Bool()) }) val c = 5.U(3.W) - val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5) + val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(5) val state = Reg(init = sIdle) when (state === sIdle) { when (io.nickel) { state := s5 } |
