diff options
| author | mergify[bot] | 2022-11-15 05:28:10 +0000 |
|---|---|---|
| committer | GitHub | 2022-11-15 05:28:10 +0000 |
| commit | b169f6db95f9778cf8968cc1042b7f810f9d8123 (patch) | |
| tree | 68f6fe715ce158f6de2c21c4747a500ce25f6db8 /src/test | |
| parent | c8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff) | |
fullModulePorts + Opaque Types Fix and Test (#2845) (#2846)
(cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589)
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/RecordSpec.scala | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala index 3414ec8a..5a5bcf67 100644 --- a/src/test/scala/chiselTests/RecordSpec.scala +++ b/src/test/scala/chiselTests/RecordSpec.scala @@ -284,6 +284,26 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils { testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo")) } + they should "work correctly with DataMirror in nested OpaqueType Records" in { + var mod: NestedRecordModule = null + ChiselStage.elaborate { mod = new NestedRecordModule; mod } + val ports = chisel3.experimental.DataMirror.fullModulePorts(mod.inst) + val expectedPorts = Seq( + ("clock", mod.inst.clock), + ("reset", mod.inst.reset), + ("io", mod.inst.io), + ("io_bar", mod.inst.io.bar), + ("io_bar", mod.inst.io.bar.k), + ("io_bar", mod.inst.io.bar.k.k), + ("io_bar", mod.inst.io.bar.k.k.elements.head._2), + ("io_foo", mod.inst.io.foo), + ("io_foo", mod.inst.io.foo.k), + ("io_foo", mod.inst.io.foo.k.k), + ("io_foo", mod.inst.io.foo.k.k.elements.head._2) + ) + ports shouldBe expectedPorts + } + they should "work correctly when connecting nested OpaqueType elements" in { val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule } nestedRecordChirrtl should include("input in : UInt<8>") |