Directions internals mega-refactor (#617)

Part 1 of mega-change in #578

Major notes:
- Input(...) and Output(...) now (effectively) recursively override their elements' directions
- Nodes given userDirection (Input, Output, Flip - what the user assigned to _that_ node) and actualDirection (Input, Output, None, but also Bidirectional and BidirectionalFlip for mostly Aggregates), because of the above (since a higher-level Input(...) can override the locally specified user direction).
- DataMirror (node reflection APIs) added to chisel3.experimental. This provides ways to query the user given direction of a node as well as the actual direction.
- checkSynthesizable replaced with requireIsHardware and requireIsChiselType and made available in chisel3.experimental.

Internal changes notes:
- toType moved into Emitter, this makes the implementation cleaner especially considering that Vec types can't be flipped in FIRRTL. This also more clearly separates Chisel frontend from FIRRTL emission.
- Direction separated from Bindings, both are now fields in Data, and all nodes are given hierarchical directions (Aggregates may be Bidirectional). The actualDirection at the Element (leaf) level should be the same as binding directions previously.
- Bindings are hierarchical, children (of a, for example, Bundle) have a ChildBinding that points to their parent. This is different than the previous scheme where Bindings only applied at the Element (leaf) level.
- Lots of small misc clean up.

Future PRs will address other parts of #578, including stricter direction checks that aren't a side-effect of this internal refactor, stricter checks and splitting of binding operations (Wire vs. WireInit), and node operations not introduced here (getType and deprecation of chiselCloneType). Since those shouldn't mess with internals, those should be much smaller.

9 files changed, 43 insertions, 28 deletions

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index b3791fd9..983039c5 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -89,7 +89,7 @@ class BlackBoxConstant(value: Int) extends BlackBox(
     Map("VALUE" -> value, "WIDTH" -> log2Ceil(value + 1))) {
   require(value >= 0, "value must be a UInt!")
   val io = IO(new Bundle {
-    val out = UInt(log2Ceil(value + 1).W).asOutput
+    val out = Output(UInt(log2Ceil(value + 1).W))
   })
 }
 
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 2baa6e48..c0538123 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -64,21 +64,21 @@ object Chisel3Components {
   }
 
   class Chisel3BundleModuleA extends Chisel3DriverModule(new Chisel3Bundle)
-  class Chisel3BundleModuleB extends Chisel3PassthroughModule((new Chisel3Bundle).flip)
+  class Chisel3BundleModuleB extends Chisel3PassthroughModule(Flipped(new Chisel3Bundle))
   class Chisel3RecordModuleA extends Chisel3DriverModule(new Chisel3Record)
-  class Chisel3RecordModuleB extends Chisel3PassthroughModule((new Chisel3Record).flip)
+  class Chisel3RecordModuleB extends Chisel3PassthroughModule(Flipped(new Chisel3Record))
 
   class Chisel3ModuleChiselBundleA extends Chisel3DriverModule(new ChiselBundle)
-  class Chisel3ModuleChiselBundleB extends Chisel3PassthroughModule((new ChiselBundle).flip)
+  class Chisel3ModuleChiselBundleB extends Chisel3PassthroughModule(Flipped(new ChiselBundle))
   class Chisel3ModuleChiselRecordA extends Chisel3DriverModule(new ChiselRecord)
-  class Chisel3ModuleChiselRecordB extends Chisel3PassthroughModule((new ChiselRecord).flip)
+  class Chisel3ModuleChiselRecordB extends Chisel3PassthroughModule(Flipped(new ChiselRecord))
 }
 
 class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
 
   "Modules defined in the Chisel._" should "successfully bulk connect in chisel3._" in {
-		import chisel3._
-		import chisel3.testers.BasicTester
+    import chisel3._
+    import chisel3.testers.BasicTester
     import CompatibilityComponents._
 
     assertTesterPasses(new BasicTester {
@@ -96,8 +96,8 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
   }
 
   "Moduless defined in the chisel3._" should "successfully bulk connect in Chisel._" in {
-		import Chisel._
-		import chisel3.testers.BasicTester
+    import Chisel._
+    import chisel3.testers.BasicTester
     import Chisel3Components._
 
     assertTesterPasses(new BasicTester {
@@ -116,8 +116,8 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
 
 
   "Bundles defined in Chisel._" should "work in chisel3._ Modules" in {
-		import chisel3._
-		import chisel3.testers.BasicTester
+    import chisel3._
+    import chisel3.testers.BasicTester
     import Chisel3Components._
 
     assertTesterPasses(new BasicTester {
@@ -135,8 +135,8 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
   }
 
   "Bundles defined in chisel3._" should "work in Chisel._ Modules" in {
-		import chisel3._
-		import chisel3.testers.BasicTester
+    import chisel3._
+    import chisel3.testers.BasicTester
     import CompatibilityComponents._
 
     assertTesterPasses(new BasicTester {
@@ -156,8 +156,8 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
 
   "Similar Bundles defined in the chisel3._ and Chisel._" should
       "successfully bulk connect in chisel3._" in {
-		import chisel3._
-		import chisel3.testers.BasicTester
+    import chisel3._
+    import chisel3.testers.BasicTester
     import Chisel3Components._
     import CompatibilityComponents._
 
@@ -187,8 +187,8 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
     })
   }
   they should "successfully bulk connect in Chisel._" in {
-		import Chisel._
-		import chisel3.testers.BasicTester
+    import Chisel._
+    import chisel3.testers.BasicTester
     import Chisel3Components._
     import CompatibilityComponents._
 
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 102653af..110cf483 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -85,8 +85,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
-        val in = UInt(32.W).asInput
-        val out = Bool().asOutput
+        val in = Input(UInt(32.W))
+        val out = Output(Bool())
       })
       io.out := io.in(1)
     }
@@ -99,8 +99,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
-          val in = UInt(32.W).asInput
-          val out = Bool().asOutput
+          val in = Input(UInt(32.W))
+          val out = Output(Bool())
         }
         io.out := io.in(1)
       }
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 83ef7088..9b353840 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -8,21 +8,34 @@ import org.scalatest.matchers._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
 
+class DirectionedBundle extends Bundle {
+  val in = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
+}
+
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
     val in = Input(UInt(32.W))
     val out = Output(UInt(32.W))
+    val inBundle = Input(new DirectionedBundle)  // should override elements
+    val outBundle = Output(new DirectionedBundle)  // should override elements
   })
 }
 
 class GoodDirection extends DirectionHaver {
   io.out := 0.U
+  io.outBundle.in := 0.U
+  io.outBundle.out := 0.U
 }
 
 class BadDirection extends DirectionHaver {
   io.in := 0.U
 }
 
+class BadSubDirection extends DirectionHaver {
+  io.inBundle.out := 0.U
+}
+
 class DirectionSpec extends ChiselPropSpec with Matchers {
 
   //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
@@ -35,5 +48,8 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
     a[Exception] should be thrownBy {
      elaborate(new BadDirection)
     }
+    a[Exception] should be thrownBy {
+     elaborate(new BadSubDirection)
+    }
   }
 }
diff --git a/src/test/scala/chiselTests/FromBitsTester.scala b/src/test/scala/chiselTests/FromBitsTester.scala
index 39d6a4fe..e916272f 100644
--- a/src/test/scala/chiselTests/FromBitsTester.scala
+++ b/src/test/scala/chiselTests/FromBitsTester.scala
@@ -5,10 +5,9 @@ package chiselTests
 import org.scalatest._
 
 import chisel3._
-import chisel3.experimental.FixedPoint
+import chisel3.experimental.{DataMirror, FixedPoint}
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.core.DataMirror
 
 class FromBitsBundleTester extends BasicTester {
   class MultiTypeBundle extends Bundle {
diff --git a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala
index bd1bade8..52ca418a 100644
--- a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala
+++ b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala
@@ -10,7 +10,7 @@ class MissingCloneBindingExceptionSpec extends ChiselFlatSpec with Matchers {
     import chisel3._
 
     class TestIO(w: Int) extends Bundle {
-      val a = Vec(4, UInt(w.W)).asInput
+      val a = Input(Vec(4, UInt(w.W)))
 
       //override def cloneType = (new TestIO(w)).asInstanceOf[this.type]
     }
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 4f043f0a..2ae8fa5e 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -60,7 +60,7 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) {
 class ModuleWhen extends Module {
   val io = IO(new Bundle {
     val s = new SimpleIO
-    val en = Bool()
+    val en = Output(Bool())
   })
   when(io.en) {
     val inc = Module(new PlusOne).io
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 3358d506..d17ff9bd 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -24,7 +24,8 @@ trait RecordSpecUtils {
     override def cloneType = (new MyBundle).asInstanceOf[this.type]
   }
   // Useful for constructing types from CustomBundle
-  val fooBarType = new CustomBundle("foo" -> UInt(32.W), "bar" -> UInt(32.W))
+  // This is a def because each call to this needs to return a new instance
+  def fooBarType = new CustomBundle("foo" -> UInt(32.W), "bar" -> UInt(32.W))
 
   class MyModule(output: => Record, input: => Record) extends Module {
     val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/ReinterpretCast.scala b/src/test/scala/chiselTests/ReinterpretCast.scala
index cd0d1fa9..61c351ab 100644
--- a/src/test/scala/chiselTests/ReinterpretCast.scala
+++ b/src/test/scala/chiselTests/ReinterpretCast.scala
@@ -5,10 +5,9 @@ package chiselTests
 import org.scalatest._
 
 import chisel3._
-import chisel3.experimental.FixedPoint
+import chisel3.experimental.{DataMirror, FixedPoint}
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.core.DataMirror
 
 class AsBundleTester extends BasicTester {
   class MultiTypeBundle extends Bundle {