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authorRichard Lin2016-02-26 12:51:13 -0800
committerRichard Lin2016-02-26 12:51:13 -0800
commita2173d2bba816d174372a5198de3af14cd908f12 (patch)
tree85b2bb4f748f4de9e94dca39b657f2c9f784cf57 /src/test
parentb7b5d8932d92ed90ef2f69e4d542bf97536f9db1 (diff)
parent2e4d7869400f121bdae692f5c5b7976b1cb58438 (diff)
Merge pull request #109 from ucb-bar/Fix-init-in-DeqIO
Fix init in deq io
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/chiselTests/VectorPacketIO.scala63
1 files changed, 63 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
new file mode 100644
index 00000000..99ec66a6
--- /dev/null
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -0,0 +1,63 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import Chisel._
+import Chisel.testers.BasicTester
+
+/**
+ * This test used to fail when assignment statements were
+ * contained in DeqIO and EnqIO constructors.
+ * The symptom is creation of a firrtl file
+ * with missing declarations, the problem is exposed by
+ * the creation of the val outs in VectorPacketIO
+ *
+ * NOTE: The problem does not exist now because the initialization
+ * code has been removed from DeqIO and EnqIO
+ *
+ * IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated.
+ */
+class Packet extends Bundle {
+ val header = UInt(width = 1)
+}
+
+/**
+ * The problem occurs with just the ins or the outs
+ * lines also.
+ * The problem does not occur if the Vec is taken out
+ */
+class VectorPacketIO(n: Int) extends Bundle {
+ val ins = Vec(n, new DeqIO(new Packet()))
+ val outs = Vec(n, new EnqIO(new Packet()))
+}
+
+/**
+ * a module uses the vector based IO bundle
+ * the value of n does not affect the error
+ */
+class BrokenVectorPacketModule extends Module {
+ val n = 4
+ val io = new VectorPacketIO(n)
+
+ /* the following method of initializing the circuit may change in the future */
+ io.outs.foreach(_.init())
+}
+
+class VectorPacketIOUnitTester extends BasicTester {
+ val device_under_test = Module(new BrokenVectorPacketModule)
+
+ // This counter just makes the test end quicker
+ val c = Counter(1)
+ when(c.inc()) {
+ stop()
+ }
+}
+
+class VectorPacketIOUnitTesterSpec extends ChiselFlatSpec {
+ "a circuit using an io containing a vector of EnqIO wrapped packets" should
+ "compile and run" in {
+ assertTesterPasses {
+ new VectorPacketIOUnitTester
+ }
+ }
+}