diff options
| author | Schuyler Eldridge | 2019-01-14 12:20:44 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-05-22 16:17:17 -0400 |
| commit | 0e6eb5b35a442edf70ad37f963526609f2ba1f3c (patch) | |
| tree | 2b24df6fd9e71a1f735d9dc1073b6bee6b1c04d2 /src/test | |
| parent | 20ba486ab1988e57e2b2ca163c9c83e1d8904bba (diff) | |
Add chisel.stage.phases.AddImplicitOutputFile
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala new file mode 100644 index 00000000..411aa6ba --- /dev/null +++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala @@ -0,0 +1,49 @@ +// See LICENSE for license details. + +package chiselTests.stage.phases + +import org.scalatest.{FlatSpec, Matchers} + +import chisel3.experimental.RawModule +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation} +import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate} + +import firrtl.AnnotationSeq +import firrtl.options.{Phase, StageOptions, TargetDirAnnotation} +import firrtl.options.Viewer.view + +class AddImplicitOutputFileSpec extends FlatSpec with Matchers { + + class Foo extends RawModule { override val desiredName = "Foo" } + + class Fixture { val phase: Phase = new AddImplicitOutputFile } + + behavior of classOf[AddImplicitOutputFile].toString + + it should "not override an existing ChiselOutputFileAnnotation" in new Fixture { + val annotations: AnnotationSeq = Seq( + ChiselGeneratorAnnotation(() => new Foo), + ChiselOutputFileAnnotation("Bar") ) + + Seq( new Elaborate, phase ) + .foldLeft(annotations)((a, p) => p.transform(a)) + .collect{ case a: ChiselOutputFileAnnotation => a.file } + .toSeq should be (Seq("Bar")) + } + + it should "generate a ChiselOutputFileAnnotation from a ChiselCircuitAnnotation" in new Fixture { + val annotations: AnnotationSeq = Seq( + ChiselGeneratorAnnotation(() => new Foo), + TargetDirAnnotation("test_run_dir") ) + + Seq( new Elaborate, phase ) + .foldLeft(annotations)((a, p) => p.transform(a)) + .collect{ case a: ChiselOutputFileAnnotation => a.file } + .toSeq should be (Seq("Foo")) + } + + it should "do nothing to an empty annotation sequence" in new Fixture { + phase.transform(AnnotationSeq(Seq.empty)).toSeq should be (empty) + } + +} |
