Remove Deprecated APIs (#1730)

4 files changed, 2 insertions, 160 deletions

diff --git a/src/test/scala/chiselTests/AsyncResetSpec.scala b/src/test/scala/chiselTests/AsyncResetSpec.scala
index a8e62fe8..d49f390c 100644
--- a/src/test/scala/chiselTests/AsyncResetSpec.scala
+++ b/src/test/scala/chiselTests/AsyncResetSpec.scala
@@ -209,7 +209,6 @@ class AsyncResetSpec extends ChiselFlatSpec with Utils {
   }
 
   it should "support Fixed regs" in {
-    import chisel3.experimental.{withReset => _, _}
     assertTesterPasses(new BasicTester {
       val reg = withReset(reset.asAsyncReset)(RegNext(-6.0.F(2.BP), 3.F(2.BP)))
       val (count, done) = Counter(true.B, 4)
@@ -223,7 +222,7 @@ class AsyncResetSpec extends ChiselFlatSpec with Utils {
   }
 
   it should "support Interval regs" in {
-    import chisel3.experimental.{withReset => _, _}
+    import chisel3.experimental._
     assertTesterPasses(new BasicTester {
       val reg = withReset(reset.asAsyncReset) {
         val x = RegInit(Interval(range"[0,13]"), 13.I)
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 6a77c821..c7a68e7c 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -103,7 +103,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       Reverse(wire) shouldBe a [UInt]
       Cat(wire, wire) shouldBe a [UInt]
       Log2(wire) shouldBe a [UInt]
-      unless(Bool(false)) {}
       // 'switch' and 'is' are tested below in Risc
       Counter(2) shouldBe a [Counter]
       DecoupledIO(wire) shouldBe a [DecoupledIO[UInt]]
@@ -353,13 +352,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
       info("Deprecated method DC hasn't been removed")
       val bp = BitPat.DC(4)
-
-      info("BitPat != UInt is a Bool")
-      (bp != UInt(4)) shouldBe a [Bool]
-
-      /* This test does not work, but I'm not sure it's supposed to? It does *not* work on chisel3. */
-      // info("UInt != BitPat is a Bool")
-      // (UInt(4) != bp) shouldBe a [Bool]
     }
 
     ChiselStage.elaborate(new Foo)
@@ -474,22 +466,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   behavior of "Data methods"
 
-  it should "support legacy methods" in {
-    class Foo extends Module {
-      val io = IO(new Bundle{})
-
-      info("litArg works")
-      UInt(width=3).litArg() should be (None)
-      UInt(0, width=3).litArg() should be (Some(chisel3.internal.firrtl.ULit(0, 3.W)))
-
-      info("toBits works")
-      val wire = Wire(UInt(width=4))
-      Vec.fill(4)(wire).toBits.getWidth should be (wire.getWidth * 4)
-    }
-
-    ChiselStage.elaborate(new Foo)
-  }
-
   behavior of "Wire"
 
   it should "support legacy methods" in {
@@ -542,9 +518,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       val u = UInt(8)
       val s = SInt(-4)
 
-      info("toBools works")
-      u.toBools shouldBe a [Seq[Bool]]
-
       info("asBits works")
       s.asBits shouldBe a [Bits]
 
@@ -553,35 +526,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
       info("toUInt works")
       s.toUInt shouldBe a [UInt]
-
-      info("toBool works")
-      UInt(1).toBool shouldBe a [Bool]
-    }
-
-    ChiselStage.elaborate(new Foo)
-  }
-
-  behavior of "UInt"
-
-  it should "support legacy methods" in {
-    class Foo extends Module {
-      val io = new Bundle{}
-
-      info("!= works")
-      (UInt(1) != UInt(1)) shouldBe a [Bool]
-    }
-
-    ChiselStage.elaborate(new Foo)
-  }
-
-  behavior of "SInt"
-
-  it should "support legacy methods" in {
-    class Foo extends Module {
-      val io = new Bundle{}
-
-      info("!= works")
-      (SInt(-1) != SInt(-1)) shouldBe a [Bool]
     }
 
     ChiselStage.elaborate(new Foo)
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
deleted file mode 100644
index 3a78683b..00000000
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests
-
-import java.io.File
-
-import chisel3._
-import firrtl.FirrtlExecutionSuccess
-import org.scalacheck.Test.Failed
-import org.scalatest.Succeeded
-import org.scalatest.freespec.AnyFreeSpec
-import org.scalatest.matchers.should.Matchers
-
-class DummyModule extends Module {
-  val io = IO(new Bundle {
-    val in = Input(UInt(1.W))
-    val out = Output(UInt(1.W))
-  })
-  io.out := io.in
-}
-
-class TypeErrorModule extends chisel3.Module {
-  val in = IO(Input(UInt(1.W)))
-  val out = IO(Output(SInt(1.W)))
-  out := in
-}
-
-class DriverSpec extends AnyFreeSpec with Matchers with chiselTests.Utils {
-  "Driver's execute methods are used to run chisel and firrtl" - {
-    "options can be picked up from comand line with no args" in {
-      // NOTE: Since we don't provide any arguments (notably, "--target-dir"),
-      //  the generated files will be created in the current directory.
-      val  targetDir = "."
-      Driver.execute(Array.empty[String], () => new DummyModule) match {
-        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val exts = List("anno.json", "fir", "v")
-          for (ext <- exts) {
-            val dummyOutput = new File(targetDir, "DummyModule" + "." + ext)
-            info(s"${dummyOutput.toString} exists")
-            dummyOutput.exists() should be(true)
-            dummyOutput.delete()
-          }
-          Succeeded
-        case _ =>
-          Failed
-      }
-    }
-
-    "options can be picked up from comand line setting top name" in {
-      val  targetDir = "local-build"
-      Driver.execute(Array("-tn", "dm", "-td", targetDir), () => new DummyModule) match {
-        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val exts = List("anno.json", "fir", "v")
-          for (ext <- exts) {
-            val dummyOutput = new File(targetDir, "dm" + "." + ext)
-            info(s"${dummyOutput.toString} exists")
-            dummyOutput.exists() should be(true)
-            dummyOutput.delete()
-          }
-          Succeeded
-        case _ =>
-          Failed
-      }
-
-    }
-
-    "execute returns a chisel execution result" in {
-      val targetDir = "test_run_dir"
-      val args = Array("--compiler", "low", "--target-dir", targetDir)
-
-      info("Driver returned a ChiselExecutionSuccess")
-      val result = Driver.execute(args, () => new DummyModule)
-      result shouldBe a[ChiselExecutionSuccess]
-
-      info("emitted circuit included 'circuit DummyModule'")
-      val successResult = result.asInstanceOf[ChiselExecutionSuccess]
-      successResult.emitted should include ("circuit DummyModule")
-
-      val dummyOutput = new File(targetDir, "DummyModule.lo.fir")
-      info(s"${dummyOutput.toString} exists")
-      dummyOutput.exists() should be(true)
-      dummyOutput.delete()
-    }
-
-    "user errors show a trimmed stack trace" in {
-      val targetDir = "test_run_dir"
-      val args = Array("--compiler", "low", "--target-dir", targetDir)
-
-      val (stdout, stderr, result) = grabStdOutErr { Driver.execute(args, () => new TypeErrorModule) }
-
-      info("stdout shows a trimmed stack trace")
-      stdout should include ("Stack trace trimmed to user code only")
-
-      info("stdout does not include FIRRTL information")
-      stdout should not include ("firrtl.")
-
-      info("Driver returned a ChiselExecutionFailure")
-      result shouldBe a [ChiselExecutionFailure]
-    }
-  }
-}
diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala
index b3534f11..06f911e6 100644
--- a/src/test/scala/chiselTests/experimental/ForceNames.scala
+++ b/src/test/scala/chiselTests/experimental/ForceNames.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import firrtl._
 import chisel3._
-import chisel3.core.annotate
+import chisel3.experimental.annotate
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util.experimental.{ForceNameAnnotation, ForceNamesTransform, InlineInstance, forceName}
 import firrtl.annotations.{Annotation, ReferenceTarget}