diff options
| author | Jiuyang Liu | 2021-11-24 03:11:25 +0800 |
|---|---|---|
| committer | GitHub | 2021-11-23 19:11:25 +0000 |
| commit | f26f8554879f638b4c4743becbc6da13da174e63 (patch) | |
| tree | 18b0a8d884c58f8b0d22ad6f52eb2918c465e798 /src/test/scala | |
| parent | 2b0bc0ecbc9c53882e2104ecd1e1387039be27f3 (diff) | |
fix for chipsalliance/firrtl#2421 (#2256)
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/chiselTests/IntervalSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala index a33cedc1..c223260d 100644 --- a/src/test/scala/chiselTests/IntervalSpec.scala +++ b/src/test/scala/chiselTests/IntervalSpec.scala @@ -15,7 +15,7 @@ import firrtl.passes.CheckTypes.InvalidConnect import firrtl.passes.CheckWidths.{DisjointSqueeze, InvalidRange} import firrtl.passes.{PassExceptions, WrapWithRemainder} import firrtl.stage.{CompilerAnnotation, FirrtlCircuitAnnotation} -import firrtl.{FIRRTLException, HighFirrtlCompiler, LowFirrtlCompiler, MiddleFirrtlCompiler, MinimumVerilogCompiler, NoneCompiler, SystemVerilogCompiler, VerilogCompiler} +import firrtl.{HighFirrtlCompiler, LowFirrtlCompiler, MiddleFirrtlCompiler, MinimumVerilogCompiler, NoneCompiler, SystemVerilogCompiler, VerilogCompiler} import org.scalatest.freespec.AnyFreeSpec import org.scalatest.matchers.should.Matchers |