diff options
| author | Schuyler Eldridge | 2019-07-31 14:19:58 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-07-31 15:53:26 -0400 |
| commit | cb7bd3e70f2864d233a32e9935af4b7a829ff0af (patch) | |
| tree | 1e0a404446e548292fb9b2f01cb1bea35ae2d2ea /src/test/scala | |
| parent | fc85e085ae525c39a24778c5e35bec87145d1652 (diff) | |
Add Data deprecated compatibility tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 7194cb3c..2fa936ed 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -463,4 +463,22 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks elaborate(new Foo) } + behavior of "Data methods" + + it should "support legacy methods" in { + class Foo extends Module { + val io = IO(new Bundle{}) + + info("litArg works") + UInt(width=3).litArg() should be (None) + UInt(0, width=3).litArg() should be (Some(chisel3.internal.firrtl.ULit(0, 3.W))) + + info("toBits works") + val wire = Wire(UInt(width=4)) + Vec.fill(4)(wire).toBits.getWidth should be (wire.getWidth * 4) + } + + elaborate(new Foo) + } + } |
