diff options
| author | mergify[bot] | 2022-04-15 19:45:25 +0000 |
|---|---|---|
| committer | GitHub | 2022-04-15 19:45:25 +0000 |
| commit | b187a0ce5269e735e7bd75620b4fd33f7ed27af5 (patch) | |
| tree | 3983b38f4111f4eba6f0797144d519081ee92a61 /src/test/scala | |
| parent | efd474842738444a030fbe7702d58d4a249d6ebc (diff) | |
Enable Clock Invalidation (#2485) (#2487)
Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa)
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/chiselTests/InvalidateAPISpec.scala | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 2c51e5d2..dbd353a0 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -228,4 +228,12 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare) firrtlOutput should include("is invalid") } + + property("a clock should be able to be connected to a DontCare") { + class ClockConnectedToDontCare extends Module { + val foo = IO(Output(Clock())) + foo := DontCare + } + myGenerateFirrtl(new ClockConnectedToDontCare) should include("foo is invalid") + } } |
