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authorHenry Cook2015-11-04 10:17:19 -0800
committerHenry Cook2015-11-04 10:17:19 -0800
commita9a889d169cd80df53fda53534c54ea9273b3708 (patch)
tree3d8627dd4e02d469641dda51c59cca25d817cdea /src/test/scala
parent7a2d099a05eefa721977794a36d38af4c39258b6 (diff)
Use elaborate for elaboration tests, not execute
Diffstat (limited to 'src/test/scala')
-rw-r--r--src/test/scala/chiselTests/Reg.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 77d10d98..55c92b45 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -18,7 +18,7 @@ class RegSpec extends ChiselFlatSpec {
val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
reg.width.get should be (2)
}
- assert(execute{new RegOutTypeWidthTester})
+ elaborate{ new RegOutTypeWidthTester }
}
"A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
@@ -30,7 +30,7 @@ class RegSpec extends ChiselFlatSpec {
val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
reg3.width.known should be (false)
}
- assert(execute{new RegUnknownWidthTester})
+ elaborate { new RegUnknownWidthTester }
}
"A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
@@ -38,6 +38,6 @@ class RegSpec extends ChiselFlatSpec {
val reg2 = Reg(init=UInt(20, width=7))
reg2.width.get should be (7)
}
- assert(execute{new RegForcedWidthTester})
+ elaborate{ new RegForcedWidthTester }
}
}