Merge branch 'master' into front_end_dependency

2 files changed, 31 insertions, 1 deletions

diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index b06f4572..bc838766 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -55,7 +55,7 @@ int main(int argc, char **argv, char **env) {
     val cppHarness = makeCppHarness(fname)
 
     make(fname)
-    verilogToCpp(target, path, Seq(), cppHarness).!
+    verilogToCpp(target, target, path, Seq(), cppHarness).!
     cppToExe(target, path).!
     (path, target)
   }
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 5239c6ba..943d9e4b 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -41,6 +41,32 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   }
 }
 
+class FunBundle extends Bundle {
+  val stuff = UInt(width = 10)
+}
+
+class ZeroModule extends Module {
+  val io = new Bundle {
+    val mem = UInt(width = 10)
+    val interrupts = Vec(2, Bool()).asInput
+    val mmio_axi = Vec(0, new FunBundle)
+    val mmio_ahb = Vec(0, new FunBundle).flip
+  }
+  
+  io.mmio_axi <> io.mmio_ahb
+  
+  io.mem := UInt(0)
+  when (io.interrupts(0)) { io.mem := UInt(1) }
+  when (io.interrupts(1)) { io.mem := UInt(2) }
+}
+
+class ZeroTester extends BasicTester {
+  val foo = Module(new ZeroModule)
+  foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) }
+  assert (foo.io.mem === UInt(2))
+  stop()
+}
+
 class VecSpec extends ChiselPropSpec {
   property("Vecs should be assignable") {
     forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) =>
@@ -55,4 +81,8 @@ class VecSpec extends ChiselPropSpec {
   property("Regs of vecs should be usable as shift registers") {
     forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
   }
+  
+  property("Dual empty Vectors") {
+    assertTesterPasses{ new ZeroTester }
+  }
 }