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authorBoyang Han2021-09-06 07:35:46 -0700
committerBoyang Han2021-09-06 07:35:46 -0700
commit89679a3c7b42f34d3b9e93dfb6972bc36b6af297 (patch)
treeabfe001c34833b26ce0f98a4168e15ecdf8d09b5 /src/test/scala
parent7cd821f5a975ff97694d39893af1d89952d37c69 (diff)
Add a test case to demonstrate the bug found in #2112
Diffstat (limited to 'src/test/scala')
-rw-r--r--src/test/scala/chiselTests/util/experimental/PlaSpec.scala16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
index 45ac012e..ced4f9dd 100644
--- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
@@ -49,6 +49,22 @@ class PlaSpec extends ChiselFlatSpec {
})
}
+ "#2112" should "be generated correctly" in {
+ assertTesterPasses(new BasicTester {
+ val table = Seq(
+ (BitPat("b0"), BitPat("b?0")),
+ (BitPat("b1"), BitPat("b?1")),
+ (BitPat("b?"), BitPat("b1?")),
+ )
+ table.foreach { case (i, o) =>
+ val (plaIn, plaOut) = pla(table)
+ plaIn := WireDefault(i.value.U(3.W))
+ chisel3.assert(plaOut === o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+ }
+ stop()
+ })
+ }
+
"A simple PLA" should "be generated correctly" in {
assertTesterPasses(new BasicTester {
val table = Seq(