Merge branch 'master' into fixedPointFromBits

2 files changed, 18 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 83f60391..8a12cd7b 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -43,6 +43,11 @@ int main(int argc, char **argv, char **env) {
     delete top;
     exit(0);
 }
+
+void vl_finish(const char* filename, int linenum, const char* hier) {
+  Verilated::flushCall();
+  exit(0);
+}
 """, ".cpp") _
 
   /** Compiles a C++ emulator from Verilog and returns the path to the
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index 4afb077a..1c2d390d 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -10,8 +10,21 @@ class StopTester() extends BasicTester {
   stop()
 }
 
+class StopImmediatelyTester extends BasicTester {
+  val cycle = Reg(init = 0.asUInt(4.W))
+  cycle := cycle + 1.U
+  when (cycle === 4.U) {
+    stop()
+  }
+  assert(cycle =/= 5.U, "Simulation did not exit upon executing stop()")
+}
+
 class StopSpec extends ChiselFlatSpec {
   "stop()" should "stop and succeed the testbench" in {
     assertTesterPasses { new StopTester }
   }
+
+  it should "end the simulation immediately" in {
+    assertTesterPasses { new StopImmediatelyTester }
+  }
 }