summaryrefslogtreecommitdiff
path: root/src/test/scala
diff options
context:
space:
mode:
authorJim Lawson2016-09-23 16:50:39 -0700
committerJim Lawson2016-09-23 16:50:39 -0700
commit3e174cc55be350a06e6e95ac6505a77167bd5a29 (patch)
tree01813d93be83432a7c13fed6b1f56d9b9b942ca0 /src/test/scala
parent9c88d767e04ac25ab72380c39f30e39c83abf563 (diff)
parent785620b1403d827986bf60c2a001d8d6f71eed72 (diff)
Merge branch 'master' into gsdt
Diffstat (limited to 'src/test/scala')
-rw-r--r--src/test/scala/chiselTests/Clock.scala22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
new file mode 100644
index 00000000..79dd2de4
--- /dev/null
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import org.scalatest.prop._
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
+
+class ClockAsUIntTester extends BasicTester {
+ assert(Bool(true).asClock.asUInt === UInt(1))
+ stop()
+}
+
+
+class ClockSpec extends ChiselPropSpec {
+ property("Bool.asClock.asUInt should pass a signal through unaltered") {
+ assertTesterPasses { new ClockAsUIntTester }
+ }
+}