diff options
| author | Jiuyang Liu | 2021-05-06 17:58:35 +0000 |
|---|---|---|
| committer | GitHub | 2021-05-06 17:58:35 +0000 |
| commit | 361e4433ac6f0db8564415f07258ae151a48affe (patch) | |
| tree | cf00c2dd210d94714f9b16dcf80e8cf665eaa107 /src/test/scala | |
| parent | 365a51a8ce692c85df60427e0562e89945d9797d (diff) | |
add ShiftRegisters to expose register inside ShiftRegister. (#1723)
* add ShiftRegisters to expose register inside ShiftRegister.
* use Seq.iter for oneline implementation.
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/chiselTests/Reg.scala | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index d86fe8b4..21334aea 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -69,3 +69,21 @@ class ShiftRegisterSpec extends ChiselPropSpec { forAll(smallPosInts) { (shift: Int) => assertTesterPasses{ new ShiftResetTester(shift) } } } } + +class ShiftsTester(n: Int) extends BasicTester { + val (cntVal, done) = Counter(true.B, n) + val start = 23.U + val srs = ShiftRegisters(cntVal + start, n) + when(RegNext(done)) { + srs.zipWithIndex.foreach{ case (data, index) => + assert(data === (23 + n - 1 - index).U) + } + stop() + } +} + +class ShiftRegistersSpec extends ChiselPropSpec { + property("ShiftRegisters should shift") { + forAll(smallPosInts) { (shift: Int) => assertTesterPasses{ new ShiftsTester(shift) } } + } +} |
