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authorJim Lawson2016-10-05 16:18:59 -0700
committerGitHub2016-10-05 16:18:59 -0700
commit0675d2443c07bbd43723bf57694b688d2df08498 (patch)
tree5566195d427b5d75031726002f6b96d5742e3c08 /src/test/scala
parent7981c6d9e6d25fb27b25e1427794775c9f934a09 (diff)
parenta18002c879d14b6c51cd49311a3b2a99a6a204fc (diff)
Merge pull request #315 from ucb-bar/fix-rocket-chip
Give <> and := legacy behavior in compatibility mode
Diffstat (limited to 'src/test/scala')
-rw-r--r--src/test/scala/chiselTests/CompileOptionsTest.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 66a9dcc0..57ceff3f 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -23,6 +23,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
val dontTryConnectionsSwapped = true
val dontAssumeDirectionality = true
val deprecateOldDirectionMethods = true
+ val checkSynthesizable = true
}
class SmallBundle extends Bundle {
@@ -267,6 +268,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
val dontTryConnectionsSwapped = true
val dontAssumeDirectionality = true
val deprecateOldDirectionMethods = false
+ val checkSynthesizable = true
}
}