diff options
| author | mergify[bot] | 2022-12-10 10:45:37 +0000 |
|---|---|---|
| committer | GitHub | 2022-12-10 10:45:37 +0000 |
| commit | 044b062468c90a1084221e480463515c668e99df (patch) | |
| tree | 16c9a9aa5fa1f795e22211cc3d50827501a5a049 /src/test/scala | |
| parent | 294bf10510b2dc55312be2e87f9bed556c68afc5 (diff) | |
Fix string interpolation in `util.exprimental.decode.bitset` (#2882) (#2883)
* Fix BitSet decoder API when errorBit=False
When errorBit is set to False, the original code will return
`Unit` which will be `()` in interpolated string.
* Add testcases for both errorBit cases in BitSetSpec
(cherry picked from commit 42416cb6c6a3019fc29b9d98cfea3e3bb4e42684)
Co-authored-by: Ocean Shen <30361859+OceanS2000@users.noreply.github.com>
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/chiselTests/util/BitSetSpec.scala | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala index dd66ba40..cf5f54cf 100644 --- a/src/test/scala/chiselTests/util/BitSetSpec.scala +++ b/src/test/scala/chiselTests/util/BitSetSpec.scala @@ -110,9 +110,36 @@ class BitSetSpec extends AnyFlatSpec with Matchers { "b11??????" ) ), - true + errorBit = true ) }) } + it should "be decoded with DontCare error" in { + import chisel3._ + import chisel3.util.experimental.decode.decoder + // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255] + // "0011????" "10??????" is empty to error + chisel3.stage.ChiselStage.emitSystemVerilog(new Module { + val in = IO(Input(UInt(8.W))) + val out = IO(Output(UInt(4.W))) + out := decoder.bitset( + in, + Seq( + BitSet.fromString( + "b000?????" + ), + BitSet.fromString( + """b0010???? + |b01?????? + |""".stripMargin + ), + BitSet.fromString( + "b11??????" + ) + ), + errorBit = false + ) + }) + } } |
