Merge pull request #1483 from freechipsproject/add-treadle-backend-for-tests

This adds a mechanism for the unittests to be run with the TreadleBac…

1 files changed, 3 insertions, 3 deletions

diff --git a/src/test/scala/examples/SimpleVendingMachine.scala b/src/test/scala/examples/SimpleVendingMachine.scala
index 2021ece8..49caa92c 100644
--- a/src/test/scala/examples/SimpleVendingMachine.scala
+++ b/src/test/scala/examples/SimpleVendingMachine.scala
@@ -3,7 +3,7 @@
 package examples
 
 import chiselTests.ChiselFlatSpec
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 import chisel3._
 import chisel3.util._
 
@@ -49,7 +49,7 @@ class FSMVendingMachine extends SimpleVendingMachine {
 }
 
 class VerilogVendingMachine extends BlackBox {
-  // Because this is a blackbox, we must explicity add clock and reset
+  // Because this is a blackbox, we must explicitly add clock and reset
   val io = IO(new SimpleVendingMachineIO {
     val clock = Input(Clock())
     val reset = Input(Reset())
@@ -90,6 +90,6 @@ class SimpleVendingMachineSpec extends ChiselFlatSpec {
   }
   "An Verilog implementation of a vending machine" should "work" in {
     assertTesterPasses(new SimpleVendingMachineTester(new VerilogVendingMachineWrapper),
-                       List("/chisel3/VerilogVendingMachine.v"))
+                       List("/chisel3/VerilogVendingMachine.v"), annotations = TesterDriver.verilatorOnly)
   }
 }