diff options
| author | Richard Lin | 2017-09-26 21:05:13 -0700 |
|---|---|---|
| committer | GitHub | 2017-09-26 21:05:13 -0700 |
| commit | e2c5c128f6509805f71aeca790809b3e9a8fe84d (patch) | |
| tree | e35c402a1cda49129dc9e6ab84c6ec3db8618215 /src/test/scala/chiselTests | |
| parent | 7af4163cb83e414a19be8484cdbb6f1b04686e99 (diff) | |
Disallow assignment to op results (#698)
Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 35 |
1 files changed, 28 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index fbe57da5..1e1d3f70 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -26,11 +26,6 @@ class LastAssignTester() extends BasicTester { } } -class ReassignmentTester() extends BasicTester { - val test = 15.U - test := 7.U -} - class MultiAssignSpec extends ChiselFlatSpec { "The last assignment" should "be used when multiple assignments happen" in { assertTesterPasses{ new LastAssignTester } @@ -38,9 +33,35 @@ class MultiAssignSpec extends ChiselFlatSpec { } class IllegalAssignSpec extends ChiselFlatSpec { - "Reassignments to non-wire types" should "be disallowed" in { + "Reassignments to literals" should "be disallowed" in { + intercept[chisel3.internal.ChiselException] { + elaborate{ new BasicTester { + 15.U := 7.U + }} + } + } + + "Reassignments to ops" should "be disallowed" in { + intercept[chisel3.internal.ChiselException] { + elaborate{ new BasicTester { + (15.U + 1.U) := 7.U + }} + } + } + + "Reassignments to bit slices" should "be disallowed" in { + intercept[chisel3.internal.ChiselException] { + elaborate{ new BasicTester { + (15.U)(1, 0) := 7.U + }} + } + } + + "Bulk-connecting two read-only nodes" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { - assertTesterFails{ new ReassignmentTester } + elaborate{ new BasicTester { + (15.U + 1.U) <> 7.U + }} } } } |
