Extend TesterDriver to optionally take in additional Verilog sources

1 files changed, 1 insertions, 1 deletions

diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 31a219e4..5c2d29d4 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -54,7 +54,7 @@ int main(int argc, char **argv, char **env) {
     val vDut = make(fname)
     val vH = new File(path + "/V" + prefix + ".h")
     val cppHarness = makeCppHarness(fname)
-    verilogToCpp(target, dir, vDut, cppHarness, vH).!
+    verilogToCpp(target, dir, vDut, Seq(), cppHarness, vH).!
     cppToExe(prefix, dir).!
     prefix
   }