Optional clock param for memory ports (#2333) (#2382)

Warn if clock at memory instantiation differs from clock bound at port
creation and port clock is not manually passed

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 465805ec7b2696a985eaa12cf9c6868f11ac2931)

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>

1 files changed, 109 insertions, 1 deletions

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 2553f3b3..381b4009 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -113,7 +113,7 @@ class MultiClockMemTest extends BasicTester {
   when(done) { stop() }
 }
 
-class MultiClockSpec extends ChiselFlatSpec {
+class MultiClockSpec extends ChiselFlatSpec with Utils {
 
   "withClock" should "scope the clock of registers" in {
     assertTesterPasses(new ClockDividerTest)
@@ -129,6 +129,114 @@ class MultiClockSpec extends ChiselFlatSpec {
     })
   }
 
+  "Differing clocks at memory and port instantiation" should "warn" in {
+    class modMemDifferingClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = withClock(myClock) { Mem(4, UInt(8.W)) }
+      val port0 = mem(0.U)
+    }
+    val (logMemDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemDifferingClock))
+    logMemDifferingClock should include("memory is different")
+
+    class modSyncReadMemDifferingClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
+      val port0 = mem(0.U)
+    }
+    val (logSyncReadMemDifferingClock, _) = grabLog(ChiselStage.elaborate(new modSyncReadMemDifferingClock))
+    logSyncReadMemDifferingClock should include("memory is different")
+  }
+
+  "Differing clocks at memory and write accessor instantiation" should "warn" in {
+    class modMemWriteDifferingClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = withClock(myClock) { Mem(4, UInt(8.W)) }
+      mem(1.U) := 1.U
+    }
+    val (logMemWriteDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemWriteDifferingClock))
+    logMemWriteDifferingClock should include("memory is different")
+
+    class modSyncReadMemWriteDifferingClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
+      mem.write(1.U, 1.U)
+    }
+    val (logSyncReadMemWriteDifferingClock, _) = grabLog(ChiselStage.elaborate(new modSyncReadMemWriteDifferingClock))
+    logSyncReadMemWriteDifferingClock should include("memory is different")
+  }
+
+  "Differing clocks at memory and read accessor instantiation" should "warn" in {
+    class modMemReadDifferingClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = withClock(myClock) { Mem(4, UInt(8.W)) }
+      val readVal = mem.read(0.U)
+    }
+    val (logMemReadDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemReadDifferingClock))
+    logMemReadDifferingClock should include("memory is different")
+
+    class modSyncReadMemReadDifferingClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
+      val readVal = mem.read(0.U)
+    }
+    val (logSyncReadMemReadDifferingClock, _) = grabLog(ChiselStage.elaborate(new modSyncReadMemReadDifferingClock))
+    logSyncReadMemReadDifferingClock should include("memory is different")
+  }
+
+  "Passing clock parameter to memory port instantiation" should "not warn" in {
+    class modMemPortClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = Mem(4, UInt(8.W))
+      val port0 = mem(0.U, myClock)
+    }
+    val (logMemPortClock, _) = grabLog(ChiselStage.elaborate(new modMemPortClock))
+    (logMemPortClock should not).include("memory is different")
+
+    class modSyncReadMemPortClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = SyncReadMem(4, UInt(8.W))
+      val port0 = mem(0.U, myClock)
+    }
+    val (logSyncReadMemPortClock, _) = grabLog(ChiselStage.elaborate(new modSyncReadMemPortClock))
+    (logSyncReadMemPortClock should not).include("memory is different")
+  }
+
+  "Passing clock parameter to memory write accessor" should "not warn" in {
+    class modMemWriteClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = Mem(4, UInt(8.W))
+      mem.write(0.U, 0.U, myClock)
+    }
+    val (logMemWriteClock, _) = grabLog(ChiselStage.elaborate(new modMemWriteClock))
+    (logMemWriteClock should not).include("memory is different")
+
+    class modSyncReadMemWriteClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = SyncReadMem(4, UInt(8.W))
+      mem.write(0.U, 0.U, myClock)
+    }
+    val (logSyncReadMemWriteClock, _) = grabLog(ChiselStage.elaborate(new modSyncReadMemWriteClock))
+    (logSyncReadMemWriteClock should not).include("memory is different")
+  }
+
+  "Passing clock parameter to memory read accessor" should "not warn" in {
+    class modMemReadClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = Mem(4, UInt(8.W))
+      val readVal = mem.read(0.U, myClock)
+    }
+    val (logMemReadClock, _) = grabLog(ChiselStage.elaborate(new modMemReadClock))
+    (logMemReadClock should not).include("memory is different")
+
+    class modSyncReadMemReadClock extends Module {
+      val myClock = IO(Input(Clock()))
+      val mem = SyncReadMem(4, UInt(8.W))
+      val readVal = mem.read(0.U, myClock)
+    }
+    val (logSyncReadMemReadClock, _) = grabLog(ChiselStage.elaborate(new modSyncReadMemReadClock))
+    (logSyncReadMemReadClock should not).include("memory is different")
+  }
+
   "withReset" should "scope the reset of registers" in {
     assertTesterPasses(new WithResetTest)
   }