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| author | Andrew Waterman | 2016-07-07 15:41:10 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-07-07 15:41:10 -0700 |
| commit | c90be4ea06faf9a39c85f38e932d29fe63eb4b37 (patch) | |
| tree | 8c9c96cf8e149edf333356d07b63f283df479e23 /src/test/scala/chiselTests | |
| parent | a49e27d1247597de5997f0fe6f3d2ac594ec2e6b (diff) | |
Improve QoR for Log2
For reasonable circuit delay, need to divide & conquer.
Diffstat (limited to 'src/test/scala/chiselTests')
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