diff options
| author | mergify[bot] | 2022-06-08 20:09:45 +0000 |
|---|---|---|
| committer | GitHub | 2022-06-08 20:09:45 +0000 |
| commit | a689c7c0dd336fe0b9db6171786993b190a700f8 (patch) | |
| tree | b914bcb25c7d1809a79aad804386cb10b2b1fa23 /src/test/scala/chiselTests | |
| parent | 9c79051866743ba5b8f922fc309abc1302ba5547 (diff) | |
Added migration for inferModuleReset (#2571) (#2573)
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d)
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala b/src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala new file mode 100644 index 00000000..3757c360 --- /dev/null +++ b/src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chiselTests + +import chisel3.stage.ChiselStage + +import org.scalatestplus.scalacheck.ScalaCheckDrivenPropertyChecks + +class MigrateCompileOptionsSpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyChecks with Utils { + import Chisel.{defaultCompileOptions => _, _} + import chisel3.RequireSyncReset + + behavior.of("Migrating infer resets") + + val migrateIR = new chisel3.CompileOptions { + val connectFieldsMustMatch = false + val declaredTypeMustBeUnbound = false + val dontTryConnectionsSwapped = false + val dontAssumeDirectionality = false + val checkSynthesizable = false + val explicitInvalidate = false + val inferModuleReset = false + + override val migrateInferModuleReset = true + } + + it should "error if migrating, but not extended RequireSyncReset" in { + implicit val options = migrateIR + class Foo extends Module { + val io = new Bundle {} + } + intercept[Exception] { + ChiselStage.elaborate(new Foo) + } + } + it should "not error if migrating, and you mix with RequireSyncReset" in { + implicit val options = migrateIR + class Foo extends Module with RequireSyncReset { + val io = new Bundle {} + } + ChiselStage.elaborate(new Foo) + } +} |
