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authorEdward Wang2018-07-15 10:32:31 -0700
committeredwardcwang2018-08-22 11:55:38 -0700
commita635ea83f772969a22e9323f82db8cf9437d39fd (patch)
tree097a8a4a992cfcd550ff038b4a03003f06ab8ba6 /src/test/scala/chiselTests
parent02d6fbbacaf5da2080dd406b98cddbdab2ab5cb1 (diff)
MixedVec: clarify dynamic indexing of heterogeneous elements
Diffstat (limited to 'src/test/scala/chiselTests')
-rw-r--r--src/test/scala/chiselTests/MixedVecSpec.scala64
1 files changed, 61 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index ca4fdf20..36798e5b 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -74,7 +74,7 @@ class MixedVecZeroEntryTester extends BasicTester {
stop()
}
-class MixedVecDynamicIndexTester(n: Int) extends BasicTester {
+class MixedVecUIntDynamicIndexTester(n: Int) extends BasicTester {
val wire = Wire(MixedVec(Seq.fill(n) { UInt() }))
val (cycle, done) = Counter(true.B, n)
@@ -92,6 +92,60 @@ class MixedVecDynamicIndexTester(n: Int) extends BasicTester {
when (done) { stop() }
}
+class MixedVecTestBundle extends Bundle {
+ val x = UInt(8.W)
+ val y = UInt(8.W)
+}
+
+class MixedVecSmallTestBundle extends Bundle {
+ val x = UInt(3.W)
+ val y = UInt(3.W)
+}
+
+class MixedVecDynamicIndexTester extends BasicTester {
+ val wire = Wire(MixedVec(Seq(UInt(8.W), SInt(8.W), Bool(), new MixedVecTestBundle, new MixedVecSmallTestBundle)))
+
+ val val0 = 163.U(8.W)
+ val val1 = (-96).S(8.W)
+ val val2 = true.B
+ val val3 = 126.U(8.W)
+ val val4 = 6.U(3.W)
+
+ wire(0) := val0
+ wire(1) := val1
+ wire(2) := val2
+ val wire3 = wire(3).asInstanceOf[MixedVecTestBundle]
+ wire3.x := val3
+ wire3.y := val3
+ val wire4 = wire(4).asInstanceOf[MixedVecSmallTestBundle]
+ wire4.x := val4
+ wire4.y := val4
+
+ val (cycle, done) = Counter(true.B, wire.length)
+ val currentData = wire(cycle)
+
+ when(cycle === 0.U) {
+ assert(currentData === val0)
+ } .elsewhen(cycle === 1.U) {
+ // We need to trim the width appropriately before calling asSInt
+ assert(currentData(7, 0).asSInt === val1)
+ } .elsewhen(cycle === 2.U) {
+ assert(currentData === val2.asUInt)
+ } .elsewhen(cycle === 3.U) {
+ val currentBundle = currentData.asTypeOf(new MixedVecTestBundle)
+ assert(currentBundle.x === val3)
+ assert(currentBundle.y === val3)
+ } .otherwise {
+ val currentBundle = currentData.asTypeOf(new MixedVecSmallTestBundle)
+ assert(currentBundle.x === val4)
+ assert(currentBundle.y === val4)
+ }
+
+ when(done) {
+ stop()
+ }
+}
+
class MixedVecFromVecTester extends BasicTester {
val wire = Wire(MixedVec(Vec(3, UInt(8.W))))
wire := MixedVecWireInit(Seq(20.U, 40.U, 80.U))
@@ -210,8 +264,12 @@ class MixedVecSpec extends ChiselPropSpec {
assertTesterPasses { new MixedVecZeroEntryTester }
}
- property("MixedVecs should be dynamically indexable") {
- assertTesterPasses{ new MixedVecDynamicIndexTester(4) }
+ property("MixedVecs of UInts should be dynamically indexable") {
+ assertTesterPasses{ new MixedVecUIntDynamicIndexTester(4) }
+ }
+
+ property("MixedVecs in general should be dynamically indexable") {
+ assertTesterPasses{ new MixedVecDynamicIndexTester }
}
property("MixedVecs should be creatable from Vecs") {