CompileOptions: add and use emitStrictConnects (#2622) (#2623)

(cherry picked from commit 11e8cc60d6268301cff352b8a1d7c4d672b5be11)

Co-authored-by: Megan Wachs <megan@sifive.com>

1 files changed, 39 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 70dcda48..1e199297 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -351,4 +351,43 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
     compile(new Top(true))
     compile(new Top(false))
   }
+
+  "A unidirectional but flipped Bundle with something close to NotStrict compileOptions, but not exactly" should "bulk connect in import chisel3._ code correctly" in {
+    object Compat {
+      import Chisel.{defaultCompileOptions => _, _}
+      // arbitrary thing to make this *not* exactly NotStrict
+      implicit val defaultCompileOptions = new chisel3.ExplicitCompileOptions.CompileOptionsClass(
+        connectFieldsMustMatch = false,
+        declaredTypeMustBeUnbound = false,
+        dontTryConnectionsSwapped = false,
+        dontAssumeDirectionality = false,
+        checkSynthesizable = false,
+        explicitInvalidate = false,
+        inferModuleReset = true // different from NotStrict, to ensure case class equivalence to NotStrict is false
+      ) {
+        override def emitStrictConnects = false
+      }
+
+      class MyBundle(extraFlip: Boolean) extends Bundle {
+        private def maybeFlip[T <: Data](t: T): T = if (extraFlip) t.flip else t
+        val foo = maybeFlip(new Bundle {
+          val bar = UInt(INPUT, width = 8)
+        })
+      }
+    }
+    import chisel3._
+    import Compat.{defaultCompileOptions => _, _}
+    class Top(extraFlip: Boolean) extends RawModule {
+      val port = IO(new MyBundle(extraFlip))
+      val wire = Wire(new MyBundle(extraFlip))
+      port <> DontCare
+      wire <> DontCare
+      port <> wire
+      wire <> port
+      port.foo <> wire.foo
+      wire.foo <> port.foo
+    }
+    compile(new Top(true))
+    compile(new Top(false))
+  }
 }