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authormergify[bot]2022-09-29 18:53:44 +0000
committerGitHub2022-09-29 18:53:44 +0000
commit5a79814631bdc8c71c5a7b4722cd43712f7ff445 (patch)
tree6a42aceb9b6002bcbeb3070c7bb98d1b17db91b4 /src/test/scala/chiselTests
parent9f1eae19445e110bb743176767f59970ce1d36b5 (diff)
Add lexical scope checks to Assert, Assume and Printf (#2706) (#2753)
(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
Diffstat (limited to 'src/test/scala/chiselTests')
-rw-r--r--src/test/scala/chiselTests/Assert.scala77
-rw-r--r--src/test/scala/chiselTests/Printf.scala39
2 files changed, 116 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index d7885a3b..5e7b6496 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -84,6 +84,64 @@ class PrintableAssumeTester extends Module {
out := in
}
+class PrintableScopeTester extends Module {
+ val in = IO(Input(UInt(8.W)))
+ val out = IO(Output(UInt(8.W)))
+ out := in
+
+ val w = Wire(UInt(8.W))
+ w := 255.U
+
+ val printableWire = cf"$w"
+ val printablePort = cf"$in"
+}
+
+class AssertPrintableWireScope extends BasicTester {
+ val mod = Module(new PrintableScopeTester)
+ assert(1.U === 2.U, mod.printableWire)
+ stop()
+}
+
+class AssertPrintablePortScope extends BasicTester {
+ val mod = Module(new PrintableScopeTester)
+ mod.in := 255.U
+ assert(1.U === 1.U, mod.printablePort)
+ stop()
+}
+
+class AssertPrintableFailingWhenScope extends BasicTester {
+ val mod = Module(new PrintableWhenScopeTester)
+ assert(1.U === 1.U, mod.printable)
+ stop()
+}
+
+class AssumePrintableWireScope extends BasicTester {
+ val mod = Module(new PrintableScopeTester)
+ assume(1.U === 1.U, mod.printableWire)
+ stop()
+}
+
+class AssumePrintablePortScope extends BasicTester {
+ val mod = Module(new PrintableScopeTester)
+ mod.in := 255.U
+ assume(1.U === 1.U, mod.printablePort)
+ stop()
+}
+
+class PrintableWhenScopeTester extends Module {
+ val in = IO(Input(UInt(8.W)))
+ val out = IO(Output(UInt(8.W)))
+
+ out := in
+
+ val w = Wire(UInt(8.W))
+ w := 255.U
+ var printable = cf""
+ when(true.B) {
+ printable = cf"$w"
+ }
+}
+
class AssertSpec extends ChiselFlatSpec with Utils {
"A failing assertion" should "fail the testbench" in {
assert(!runTester { new FailingAssertTester })
@@ -94,6 +152,25 @@ class AssertSpec extends ChiselFlatSpec with Utils {
"An assertion" should "not assert until we come out of reset" in {
assertTesterPasses { new PipelinedResetTester }
}
+
+ "Assert Printables" should "respect port scoping" in {
+ assertTesterPasses { new AssertPrintablePortScope }
+ }
+ "Assert Printables" should "respect wire scoping" in {
+ a[ChiselException] should be thrownBy { ChiselStage.elaborate(new AssertPrintableWireScope) }
+ }
+ "Assume Printables" should "respect port scoping" in {
+ assertTesterPasses { new AssumePrintablePortScope }
+ }
+
+ "Assume Printables" should "respect wire scoping" in {
+ a[ChiselException] should be thrownBy { ChiselStage.elaborate(new AssumePrintableWireScope) }
+ }
+
+ "Assert Printables" should "respect when scope" in {
+ a[ChiselException] should be thrownBy { ChiselStage.elaborate(new AssertPrintableFailingWhenScope) }
+ }
+
"Assertions" should "allow the modulo operator % in the message" in {
assertTesterPasses { new ModuloAssertTester }
}
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 4171f97f..6c9f05f0 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -4,6 +4,7 @@ package chiselTests
import chisel3._
import chisel3.testers.BasicTester
+import chisel3.stage.ChiselStage
class SinglePrintfTester() extends BasicTester {
val x = 254.U
@@ -28,6 +29,38 @@ class ASCIIPrintableTester extends BasicTester {
stop()
}
+class ScopeTesterModule extends Module {
+ val in = IO(Input(UInt(8.W)))
+ val out = IO(Output(UInt(8.W)))
+ out := in
+
+ val w = Wire(UInt(8.W))
+ w := 125.U
+
+ val p = cf"$in"
+ val wp = cf"$w"
+}
+
+class PrintablePrintfScopeTester extends BasicTester {
+ ChiselStage.elaborate {
+ new Module {
+ val mod = Module(new ScopeTesterModule)
+ printf(mod.p)
+ }
+ }
+ stop()
+}
+
+class PrintablePrintfWireScopeTester extends BasicTester {
+ ChiselStage.elaborate {
+ new Module {
+ val mod = Module(new ScopeTesterModule)
+ printf(mod.wp)
+ }
+ }
+ stop()
+}
+
class PrintfSpec extends ChiselFlatSpec {
"A printf with a single argument" should "run" in {
assertTesterPasses { new SinglePrintfTester }
@@ -41,4 +74,10 @@ class PrintfSpec extends ChiselFlatSpec {
"A printf with Printable ASCII characters 1-127" should "run" in {
assertTesterPasses { new ASCIIPrintableTester }
}
+ "A printf with Printable" should "respect port scopes" in {
+ assertTesterPasses { new PrintablePrintfScopeTester }
+ }
+ "A printf with Printable" should "respect wire scopes" in {
+ a[ChiselException] should be thrownBy { assertTesterPasses { new PrintablePrintfWireScopeTester } }
+ }
}