Scalastyle fixes - whitespace or comments only.

9 files changed, 30 insertions, 30 deletions

diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index b19fe3d9..6600df2a 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -29,7 +29,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
   for (t <- 0 until 16) {
     val in    = rnd.nextInt(16)
     val shift = rnd.nextInt(2)
-    println("SHIFT " + shift + " IN " + in)
+    println("SHIFT " + shift + " IN " + in)   // scalastyle:ignore regex
     poke(c.io.in,    in)
     poke(c.io.shift, shift)
     step(1)
@@ -44,7 +44,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
 */
 
 class EnableShiftRegisterSpec extends ChiselPropSpec {
-  
+
   property("EnableShiftRegister should elaborate") {
     elaborate { new EnableShiftRegister }
   }
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index dcc3a403..ed76a296 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -10,8 +10,8 @@ class LFSR16 extends Module {
     val out = UInt(OUTPUT, 16)
   }
   val res = Reg(init = UInt(1, 16))
-  when (io.inc) { 
-    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) 
+  when (io.inc) {
+    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
     res := nxt_res
   }
   io.out := res
@@ -37,7 +37,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 //TODO: Use chisel.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
-  
+
   property("LFSR16 should elaborate") {
     elaborate { new LFSR16 }
   }
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index ec48c666..55b704a0 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -41,14 +41,14 @@ class MemorySearchTester(c: MemorySearch) extends Tester(c) {
       step(1)
     } while (peek(c.io.done) == 0 && t < maxT)
     val addr = peek(c.io.address).toInt
-    expect(addr == list.length || list(addr) == target, 
+    expect(addr == list.length || list(addr) == target,
            "LOOKING FOR " + target + " FOUND " + addr)
   }
 }
 */
 
 class MemorySearchSpec extends ChiselPropSpec {
-  
+
   property("MemorySearch should elaborate") {
     elaborate { new EnableShiftRegister }
   }
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 4191eea7..27fd5125 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -21,7 +21,7 @@ class ModuleVec(val n: Int) extends Module {
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
     pluses(i).in := io.ins(i)
-    io.outs(i)   := pluses(i).out 
+    io.outs(i)   := pluses(i).out
   }
 }
 
@@ -29,10 +29,10 @@ class ModuleVec(val n: Int) extends Module {
 class ModuleVecTester(c: ModuleVec) extends Tester(c) {
   for (t <- 0 until 16) {
     val test_ins = Array.fill(c.n){ rnd.nextInt(256) }
-    for (i <- 0 until c.n) 
+    for (i <- 0 until c.n)
       poke(c.io.ins(i), test_ins(i))
     step(1)
-    for (i <- 0 until c.n) 
+    for (i <- 0 until c.n)
       expect(c.io.outs(i), test_ins(i) + 1)
   }
 }
@@ -42,7 +42,7 @@ class ModuleWire extends Module {
   val io = new SimpleIO
   val inc = Wire(Module(new PlusOne).io)
   inc.in := io.in
-  io.out := inc.out 
+  io.out := inc.out
 }
 
 /*
@@ -61,27 +61,27 @@ class ModuleWhen extends Module {
     val s = new SimpleIO
     val en = Bool()
   }
-  when(io.en) { 
+  when(io.en) {
     val inc = Module(new PlusOne).io
     inc.in := io.s.in
-    io.s.out := inc.out 
+    io.s.out := inc.out
   } otherwise { io.s.out := io.s.in }
 }
 
 class ModuleSpec extends ChiselPropSpec {
-  
+
   property("ModuleVec should elaborate") {
     elaborate { new ModuleVec(2) }
   }
 
   ignore("ModuleVecTester should return the correct result") { }
-  
+
   property("ModuleWire should elaborate") {
     elaborate { new ModuleWire }
   }
 
   ignore("ModuleWireTester should return the correct result") { }
-  
+
   property("ModuleWhen should elaborate") {
     elaborate { new ModuleWhen }
   }
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 35a4c4a6..93a2c39f 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -32,7 +32,7 @@ class PadsTester(c: Pads) extends Tester(c) {
 */
 
 class PadderSpec extends ChiselPropSpec {
-  
+
   property("Padder should elaborate") {
     elaborate { new Padder }
   }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index b33b896b..ad5cf762 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -15,7 +15,7 @@ class Risc extends Module {
   val file = Mem(Bits(width = 32), 256)
   val code = Mem(Bits(width = 32), 256)
   val pc   = Reg(init=UInt(0, 8))
-  
+
   val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
 
   val inst = code(pc)
@@ -72,7 +72,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
     // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue()
     val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
-    println("I = " + cr)
+    println("I = " + cr)    // scalastyle:ignore regex
     cr
   }
 
@@ -81,10 +81,10 @@ class RiscTester(c: Risc) extends Tester(c) {
                    I(c.add_op,   1, 1, 1), // r1 <- r1 + r1
                    I(c.add_op, 255, 1, 0)) // rh <- r1
   wr(0, 0) // skip reset
-  for (addr <- 0 until app.length) 
+  for (addr <- 0 until app.length)
     wr(addr, app(addr))
   def dump(k: Int) {
-    println("K = " + k)
+    println("K = " + k)  // scalastyle:ignore regex
     peek(c.ra)
     peek(c.rb)
     peek(c.rc)
@@ -110,7 +110,7 @@ class RiscTester(c: Risc) extends Tester(c) {
 */
 
 class RiscSpec extends ChiselPropSpec {
-  
+
   property("Risc should elaborate") {
     elaborate { new Risc }
   }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 4a87a2d2..0835fb4d 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -29,7 +29,7 @@ class SIntOps extends Module {
 
   io.addout := a +% b
   io.subout := a -% b
-  // TODO: 
+  // TODO:
   //io.timesout := (a * b)(15, 0)
   //io.divout := a / Mux(b === SInt(0), SInt(1), b)
   //io.divout := (a / b)(15, 0)
@@ -83,7 +83,7 @@ class SIntOpsTester(c: SIntOps) extends Tester(c) {
 */
 
 class SIntOpsSpec extends ChiselPropSpec {
-  
+
   property("SIntOps should elaborate") {
     elaborate { new SIntOps }
   }
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0110550d..600934aa 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -14,7 +14,7 @@ class ChiselStack(val depth: Int) extends Module {
   }
 
   val stack_mem = Mem(UInt(width = 32), depth)
-  val sp        = Reg(init = UInt(0, width = log2Up(depth+1)))
+  val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
@@ -66,7 +66,7 @@ class StackTester(c: Stack) extends Tester(c) {
 */
 
 class StackSpec extends ChiselPropSpec {
-  
+
   property("Stack should elaborate") {
     elaborate { new ChiselStack(2) }
   }
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 9affb511..24cb8fc9 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -32,7 +32,7 @@ class UIntOps extends Module {
   io.timesout := (a * b)(15, 0)
   io.divout := a / Mux(b === UInt(0), UInt(1), b)
   // io.modout := a % b
-  // TODO: 
+  // TODO:
   io.modout := UInt(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
@@ -48,13 +48,13 @@ class UIntOps extends Module {
 class UIntOpsTester(c: UIntOps) extends Tester(c) {
   def uintExpect(d: Bits, x: BigInt) {
     val mask = (1 << 16) - 1
-    println(" E = " + x + " X&M = " + (x & mask))
+    println(" E = " + x + " X&M = " + (x & mask))  // scalastyle:ignore regex
     expect(d, x & mask)
   }
   for (t <- 0 until 16) {
     val test_a = rnd.nextInt(1 << 16)
     val test_b = rnd.nextInt(1 << 16)
-    println("A = " + test_a + " B = " + test_b)
+    println("A = " + test_a + " B = " + test_b)  // scalastyle:ignore regex
     poke(c.io.a, test_a)
     poke(c.io.b, test_b)
     step(1)
@@ -99,7 +99,7 @@ class UIntOpsSpec extends ChiselPropSpec with Matchers {
   property("Bools cannot be created from >1 bit UInts") {
     a [Exception] should be thrownBy { elaborate(new BadBoolConversion) }
   }
-  
+
   property("UIntOps should elaborate") {
     elaborate { new UIntOps }
   }