diff options
| author | Schuyler Eldridge | 2020-06-23 16:49:05 -0400 |
|---|---|---|
| committer | GitHub | 2020-06-23 20:49:05 +0000 |
| commit | 369bb6ece49dfb75de2a1d7784298477d60e7bcb (patch) | |
| tree | 687b0da7fc8331ec862af588ed72ee3a032fe4b9 /src/test/scala/chiselTests | |
| parent | 9f44b593efe4830aeb56d17f5ed59277a74832f8 (diff) | |
Don't run FIRRTL in FlattenSpec's ChiselStage (#1493)
Fix a bug in FlattenSpec where ChiselStage was running the FIRRTL
compiler in ChiselStage and then re-running the FIRRTL compiler. This
changes it to be like InlineSpec and to not run FIRRTL during
ChiselStage.
This was manually backported to 3.3.x.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/InlineSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala index 2d9bd792..fae927ec 100644 --- a/src/test/scala/chiselTests/InlineSpec.scala +++ b/src/test/scala/chiselTests/InlineSpec.scala @@ -72,7 +72,7 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers { "should compile to low FIRRTL" - { val chiselAnnotations = chiselStage - .execute(Array("-X", "low", "--target-dir", "test_run_dir"), + .execute(Array("--no-run-firrtl", "--target-dir", "test_run_dir"), Seq(ChiselGeneratorAnnotation(() => new Top))) chiselAnnotations.collect{ case a: FlattenAnnotation => a} should have length(1) |