Rewrite BlackBox IO contract, replace _clock|_reset

The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).

Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.

As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.

Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)

However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.

PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.

1 files changed, 51 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 574a6335..ca94087c 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -21,6 +21,14 @@ class BlackBoxPassthrough extends BlackBox {
   }
 }
 
+class BlackBoxRegister extends BlackBox {
+  val io = new Bundle() {
+    val clock = Clock().asInput
+    val in = Bool(INPUT)
+    val out = Bool(OUTPUT)
+  }
+}
+
 class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
@@ -56,6 +64,45 @@ class MultiBlackBoxTester extends BasicTester {
   stop()
 }
 
+class BlackBoxWithClockTester extends BasicTester {
+  val blackBox = Module(new BlackBoxRegister)
+  val model = Reg(Bool())
+
+  val (cycles, end) = Counter(Bool(true), 15)
+
+  val impetus = cycles(0)
+  blackBox.io.clock := clock
+  blackBox.io.in := impetus
+  model := impetus
+
+  when(cycles > UInt(0)) {
+    assert(blackBox.io.out === model)
+  }
+  when(end) { stop() }
+}
+
+/*
+// Must determine how to handle parameterized Verilog
+class BlackBoxConstant(value: Int) extends BlackBox {
+  val io = new Bundle() {
+    val out = UInt(width=log2Up(value)).asOutput
+  }
+  override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
+}
+
+class BlackBoxWithParamsTester extends BasicTester {
+  val blackBoxOne  = Module(new BlackBoxConstant(1))
+  val blackBoxFour = Module(new BlackBoxConstant(4))
+
+  val (cycles, end) = Counter(Bool(true), 4)
+
+  assert(blackBoxOne.io.out  === UInt(1))
+  assert(blackBoxFour.io.out === UInt(4))
+
+  when(end) { stop() }
+}
+*/
+
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
     assertTesterPasses({ new BlackBoxTester },
@@ -65,4 +112,8 @@ class BlackBoxSpec extends ChiselFlatSpec {
     assertTesterPasses({ new MultiBlackBoxTester },
         Seq("/BlackBoxTest.v"))
   }
+  "A BlackBoxed register" should "work" in {
+    assertTesterPasses({ new BlackBoxWithClockTester },
+        Seq("/BlackBoxTest.v"))
+  }
 }