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authorJim Lawson2016-07-27 10:29:13 -0700
committerJim Lawson2016-07-27 10:29:13 -0700
commit089987c3e0b2bc390935a4d9d44db38a18c47901 (patch)
treee7715b1fe448b7d47b8ba4de165d3c4a9e2681a9 /src/test/scala/chiselTests
parent87d69afd1c8f28d91c78e7a539f6bf7a908e2a1f (diff)
Correct EnqIO/DeqIO Flipped-ness.
Diffstat (limited to 'src/test/scala/chiselTests')
-rw-r--r--src/test/scala/chiselTests/VectorPacketIO.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 86c0d66f..b8e3a154 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -41,8 +41,8 @@ class BrokenVectorPacketModule extends Module {
val io = IO(new VectorPacketIO(n))
/* the following method of initializing the circuit may change in the future */
- io.ins.foreach(_.noenq())
- io.outs.foreach(_.nodeq())
+ io.ins.foreach(_.nodeq())
+ io.outs.foreach(_.noenq())
}
class VectorPacketIOUnitTester extends BasicTester {