Merge branch 'master' into 3.5-release

3 files changed, 154 insertions, 6 deletions

diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala
index 0c83493f..549e8bca 100644
--- a/src/test/scala/chiselTests/util/BitPatSpec.scala
+++ b/src/test/scala/chiselTests/util/BitPatSpec.scala
@@ -24,10 +24,18 @@ class BitPatSpec extends AnyFlatSpec with Matchers {
     intercept[IllegalArgumentException]{BitPat("b")}
   }
 
-  it should "contact BitPat via ##" in {
+  it should "concat BitPat via ##" in {
     (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be (s"BitPat(1111???00)")
   }
 
+  it should "throw when BitPat apply to a Hardware" in {
+    intercept[java.lang.IllegalArgumentException]{
+      chisel3.stage.ChiselStage.emitChirrtl(new chisel3.Module {
+        BitPat(chisel3.Reg(chisel3.Bool()))
+      })
+    }
+  }
+
   it should "index and return new BitPat" in {
     val b = BitPat("b1001???")
     b(0) should be(BitPat.dontCare(1))
diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala
new file mode 100644
index 00000000..8120cc97
--- /dev/null
+++ b/src/test/scala/chiselTests/util/BitSetSpec.scala
@@ -0,0 +1,119 @@
+package chiselTests.util
+
+import chisel3.util.experimental.BitSet
+import chisel3.util.BitPat
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+class BitSetSpec extends AnyFlatSpec with Matchers {
+  behavior of classOf[BitSet].toString
+
+  it should "reject unequal width when constructing a BitSet" in {
+    intercept[IllegalArgumentException] {
+      BitSet.fromString(
+        """b0010
+          |b00010
+          |""".stripMargin)
+    }
+  }
+
+  it should "return empty subtraction result correctly" in {
+    val aBitPat = BitPat("b10?")
+    val bBitPat = BitPat("b1??")
+
+    aBitPat.subtract(bBitPat).isEmpty should be (true)
+  }
+
+  it should "return nonempty subtraction result correctly" in {
+    val aBitPat = BitPat("b10?")
+    val bBitPat = BitPat("b1??")
+    val cBitPat = BitPat("b11?")
+    val dBitPat = BitPat("b100")
+
+    val diffBitPat = bBitPat.subtract(aBitPat)
+    bBitPat.cover(diffBitPat) should be (true)
+    diffBitPat.equals(cBitPat) should be (true)
+
+    val largerdiffBitPat = bBitPat.subtract(dBitPat)
+    aBitPat.cover(dBitPat) should be (true)
+    largerdiffBitPat.cover(diffBitPat) should be (true)
+  }
+
+  it should "be able to handle complex subtract between BitSet" in {
+    val aBitSet = BitSet.fromString(
+      """b?01?0
+        |b11111
+        |b00000
+        |""".stripMargin)
+    val bBitSet = BitSet.fromString(
+      """b?1111
+        |b?0000
+        |""".stripMargin
+    )
+    val expected = BitPat("b?01?0")
+
+    expected.equals(aBitSet.subtract(bBitSet)) should be (true)
+  }
+
+  it should "be generated from BitPat union" in {
+    val aBitSet = BitSet.fromString(
+      """b001?0
+        |b000??""".stripMargin)
+    val aBitPat = BitPat("b000??")
+    val bBitPat = BitPat("b001?0")
+    val cBitPat = BitPat("b00000")
+    aBitPat.cover(cBitPat) should be (true)
+    aBitSet.cover(bBitPat) should be (true)
+
+    aBitSet.equals(aBitPat.union(bBitPat)) should be (true)
+  }
+
+  it should "be generated from BitPat subtraction" in {
+    val aBitSet = BitSet.fromString(
+      """b001?0
+        |b000??""".stripMargin)
+    val aBitPat = BitPat("b00???")
+    val bBitPat = BitPat("b001?1")
+
+    aBitSet.equals(aBitPat.subtract(bBitPat)) should be (true)
+  }
+
+  it should "union two BitSet together" in {
+    val aBitSet = BitSet.fromString(
+      """b001?0
+        |b001?1
+        |""".stripMargin)
+    val bBitSet = BitSet.fromString(
+      """b000??
+        |b01???
+        |""".stripMargin
+    )
+    val cBitPat = BitPat("b0????")
+    cBitPat.equals(aBitSet.union(bBitSet)) should be (true)
+  }
+
+  it should "be decoded" in {
+    import chisel3._
+    import chisel3.util.experimental.decode.decoder
+    // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255]
+    // "0011????" "10??????" is empty to error
+    chisel3.stage.ChiselStage.emitSystemVerilog(new Module {
+      val in = IO(Input(UInt(8.W)))
+      val out = IO(Output(UInt(4.W)))
+      out := decoder.bitset(in, Seq(
+        BitSet.fromString(
+          "b000?????"
+        ),
+        BitSet.fromString(
+          """b0010????
+            |b01??????
+            |""".stripMargin
+        ),
+        BitSet.fromString(
+          "b11??????"
+        )
+      ), true)
+    })
+  }
+
+}
diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
index 743a3cd8..255effaf 100644
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests.util.experimental
 
+import chisel3._
 import chisel3.util.BitPat
-import chisel3.util.experimental.decode.TruthTable
+import chisel3.util.experimental.decode.{TruthTable, decoder}
 import org.scalatest.flatspec.AnyFlatSpec
 
 class TruthTableSpec extends AnyFlatSpec {
@@ -34,16 +35,16 @@ class TruthTableSpec extends AnyFlatSpec {
     assert(table.toString contains "     0")
   }
   "TruthTable" should "deserialize" in {
-    assert(TruthTable(str) == table)
+    assert(TruthTable.fromString(str) == table)
   }
   "TruthTable" should "merge same key" in {
     assert(
-      TruthTable(
+      TruthTable.fromString(
         """001100->??1
           |001100->1??
           |???
           |""".stripMargin
-      ) == TruthTable(
+      ) == TruthTable.fromString(
         """001100->1?1
           |???
           |""".stripMargin
@@ -52,7 +53,7 @@ class TruthTableSpec extends AnyFlatSpec {
   }
   "TruthTable" should "crash when merging 0 and 1" in {
     intercept[IllegalArgumentException] {
-      TruthTable(
+      TruthTable.fromString(
         """0->0
           |0->1
           |???
@@ -60,4 +61,24 @@ class TruthTableSpec extends AnyFlatSpec {
       )
     }
   }
+  "TruthTable" should "be reproducible" in {
+    class Foo extends Module {
+
+      val io = IO(new Bundle{
+        val in = Input(UInt(4.W))
+        val out = Output(UInt(16.W))
+      })
+
+
+      val table = TruthTable(
+        (0 until 16).map{
+          i => BitPat(i.U(4.W)) -> BitPat((1<<i).U(16.W))
+        },
+        BitPat.dontCare(16)
+      )
+
+      io.out := decoder.qmc(io.in, table)
+    }
+    assert(chisel3.stage.ChiselStage.emitChirrtl(new Foo) == chisel3.stage.ChiselStage.emitChirrtl(new Foo))
+  }
 }