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authorJack Koenig2021-01-21 22:50:12 -0800
committerGitHub2021-01-21 22:50:12 -0800
commitdd6871b8b3f2619178c2a333d9d6083805d99e16 (patch)
tree825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/test/scala/chiselTests/util
parent616256c35cb7de8fcd97df56af1986b747abe54d (diff)
parent53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff)
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/util')
-rw-r--r--src/test/scala/chiselTests/util/CatSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
index 2e52fe63..5565ca51 100644
--- a/src/test/scala/chiselTests/util/CatSpec.scala
+++ b/src/test/scala/chiselTests/util/CatSpec.scala
@@ -10,7 +10,7 @@ import chiselTests.ChiselFlatSpec
object CatSpec {
- class JackIsATypeSystemGod extends MultiIOModule {
+ class JackIsATypeSystemGod extends Module {
val in = IO(Input (Vec(0, UInt(8.W))))
val out = IO(Output(UInt(8.W)))