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| author | Jack Koenig | 2019-05-09 18:35:10 -0500 |
|---|---|---|
| committer | Andrew Waterman | 2019-05-09 16:35:10 -0700 |
| commit | 6be76f79f873873497e40fa647f9456391b4d59a (patch) | |
| tree | 0660351d647f39baefa3b76180fd4dbb53d0285c /src/test/scala/chiselTests/util | |
| parent | a9bf10cc40a5acf0f4bfb43744f9e12e8e1a0e25 (diff) | |
Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)
* IO(Analog) fixed for RawModule
* Add a Analog Port for RawModule test & spec
* Fixes around Module instantiation and ports in AnalogPortRawModuleTest
* Shorten Comment
* Add Data.isSynthesizable to distinguish SampleElementBinding
This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)
* Fix pretty printing for Vec
* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
Diffstat (limited to 'src/test/scala/chiselTests/util')
0 files changed, 0 insertions, 0 deletions