cleanup

2 files changed, 0 insertions, 237 deletions

diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
deleted file mode 100644
index 156249a2..00000000
--- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
+++ /dev/null
@@ -1,111 +0,0 @@
-package chiselTests.util.experimental
-
-import chisel3._
-import chisel3.stage.PrintFullStackTraceAnnotation
-import chisel3.testers.BasicTester
-import chisel3.util.{pla, BitPat}
-import chiselTests.ChiselFlatSpec
-
-class PlaSpec extends ChiselFlatSpec {
-  "A 1-of-8 decoder (eg. 74xx138 without enables)" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b000"), BitPat("b00000001")),
-        (BitPat("b001"), BitPat("b00000010")),
-        (BitPat("b010"), BitPat("b00000100")),
-        (BitPat("b011"), BitPat("b00001000")),
-        (BitPat("b100"), BitPat("b00010000")),
-        (BitPat("b101"), BitPat("b00100000")),
-        (BitPat("b110"), BitPat("b01000000")),
-        (BitPat("b111"), BitPat("b10000000"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table)
-          plaIn := WireDefault(i.value.U(3.W))
-          chisel3.assert(
-            plaOut === o.value.U(8.W),
-            "Input " + i.toString + " produced incorrect output BitPat(%b)",
-            plaOut
-          )
-      }
-      stop()
-    })
-  }
-
-  "An active-low 1-of-8 decoder (eg. inverted 74xx138 without enables)" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b000"), BitPat("b00000001")),
-        (BitPat("b001"), BitPat("b00000010")),
-        (BitPat("b010"), BitPat("b00000100")),
-        (BitPat("b011"), BitPat("b00001000")),
-        (BitPat("b100"), BitPat("b00010000")),
-        (BitPat("b101"), BitPat("b00100000")),
-        (BitPat("b110"), BitPat("b01000000")),
-        (BitPat("b111"), BitPat("b10000000"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table, BitPat("b11111111"))
-          plaIn := WireDefault(i.value.U(3.W))
-          chisel3.assert(
-            plaOut === ~o.value.U(8.W),
-            "Input " + i.toString + " produced incorrect output BitPat(%b)",
-            plaOut
-          )
-      }
-      stop()
-    })
-  }
-
-  "#2112" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b000"), BitPat("b?01")),
-        (BitPat("b111"), BitPat("b?01"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table)
-          plaIn := WireDefault(i.value.U(3.W))
-          chisel3.assert(o === plaOut, "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
-      }
-      stop()
-    })
-  }
-
-  "A simple PLA" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b0000"), BitPat("b1")),
-        (BitPat("b0001"), BitPat("b1")),
-        (BitPat("b0010"), BitPat("b0")),
-        (BitPat("b0011"), BitPat("b1")),
-        (BitPat("b0100"), BitPat("b1")),
-        (BitPat("b0101"), BitPat("b0")),
-        (BitPat("b0110"), BitPat("b0")),
-        (BitPat("b0111"), BitPat("b0")),
-        (BitPat("b1000"), BitPat("b0")),
-        (BitPat("b1001"), BitPat("b0")),
-        (BitPat("b1010"), BitPat("b1")),
-        (BitPat("b1011"), BitPat("b0")),
-        (BitPat("b1100"), BitPat("b0")),
-        (BitPat("b1101"), BitPat("b1")),
-        (BitPat("b1110"), BitPat("b1")),
-        (BitPat("b1111"), BitPat("b1"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table)
-          plaIn := WireDefault(i.value.U(4.W))
-          chisel3.assert(
-            plaOut === o.value.U(1.W),
-            "Input " + i.toString + " produced incorrect output BitPat(%b)",
-            plaOut
-          )
-      }
-      stop()
-    })
-  }
-}
diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
deleted file mode 100644
index b5dcee6b..00000000
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ /dev/null
@@ -1,126 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.experimental
-
-import chisel3._
-import chisel3.util.BitPat
-import chisel3.util.experimental.decode.{decoder, TruthTable}
-import org.scalatest.flatspec.AnyFlatSpec
-
-class TruthTableSpec extends AnyFlatSpec {
-  val table = TruthTable(
-    Map(
-      // BitPat("b000") -> BitPat("b0"),
-      BitPat("b001") -> BitPat("b?"),
-      BitPat("b010") -> BitPat("b?"),
-      // BitPat("b011") -> BitPat("b0"),
-      BitPat("b100") -> BitPat("b1"),
-      BitPat("b101") -> BitPat("b1"),
-      // BitPat("b110") -> BitPat("b0"),
-      BitPat("b111") -> BitPat("b1")
-    ),
-    BitPat("b0")
-  )
-  val str = """001->?
-              |010->?
-              |100->1
-              |101->1
-              |111->1
-              |0""".stripMargin
-  "TruthTable" should "serialize" in {
-    assert(table.toString contains "001->?")
-    assert(table.toString contains "010->?")
-    assert(table.toString contains "100->1")
-    assert(table.toString contains "111->1")
-    assert(table.toString contains "     0")
-  }
-  "TruthTable" should "deserialize" in {
-    val table2 = TruthTable.fromString(str)
-    assert(table2 === table)
-    assert(table2.hashCode === table.hashCode)
-  }
-  "TruthTable" should "merge same key" in {
-    assert(
-      TruthTable.fromString(
-        """001100->??1
-          |001100->1??
-          |???
-          |""".stripMargin
-      ) == TruthTable.fromString(
-        """001100->1?1
-          |???
-          |""".stripMargin
-      )
-    )
-  }
-  "TruthTable" should "crash when merging 0 and 1" in {
-    intercept[IllegalArgumentException] {
-      TruthTable.fromString(
-        """0->0
-          |0->1
-          |???
-          |""".stripMargin
-      )
-    }
-  }
-  "TruthTable" should "be reproducible" in {
-    class Foo extends Module {
-
-      val io = IO(new Bundle {
-        val in = Input(UInt(4.W))
-        val out = Output(UInt(16.W))
-      })
-
-      val table = TruthTable(
-        (0 until 16).map { i =>
-          BitPat(i.U(4.W)) -> BitPat((1 << i).U(16.W))
-        },
-        BitPat.dontCare(16)
-      )
-
-      io.out := decoder.qmc(io.in, table)
-    }
-    assert(chisel3.stage.ChiselStage.emitChirrtl(new Foo) == chisel3.stage.ChiselStage.emitChirrtl(new Foo))
-  }
-  "TruthTable" should "accept unknown input width" in {
-    val t = TruthTable(
-      Seq(
-        BitPat(0.U) -> BitPat.dontCare(1),
-        BitPat(1.U) -> BitPat.dontCare(1),
-        BitPat(2.U) -> BitPat.dontCare(1),
-        BitPat(3.U) -> BitPat.dontCare(1),
-        BitPat(4.U) -> BitPat.dontCare(1),
-        BitPat(5.U) -> BitPat.dontCare(1),
-        BitPat(6.U) -> BitPat.dontCare(1),
-        BitPat(7.U) -> BitPat.dontCare(1)
-      ),
-      BitPat.N(1)
-    )
-    assert(t.toString contains "000->?")
-    assert(t.toString contains "001->?")
-    assert(t.toString contains "010->?")
-    assert(t.toString contains "011->?")
-    assert(t.toString contains "100->?")
-    assert(t.toString contains "101->?")
-    assert(t.toString contains "110->?")
-    assert(t.toString contains "111->?")
-    assert(t.toString contains "     0")
-  }
-
-  "Using TruthTable.fromEspressoOutput" should "merge rows on conflict" in {
-    val mapping = List(
-      (BitPat("b110"), BitPat("b001")),
-      (BitPat("b111"), BitPat("b001")),
-      (BitPat("b111"), BitPat("b010")),
-      (BitPat("b111"), BitPat("b100"))
-    )
-
-    assert(
-      TruthTable.fromEspressoOutput(mapping, BitPat("b?")) ==
-        TruthTable.fromString("""110->001
-                                |111->111
-                                |?
-                                |""".stripMargin)
-    )
-  }
-}