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authorJack2022-03-15 19:37:37 +0000
committerJack2022-03-15 19:37:37 +0000
commit2f21943ff772da2171df866d4cee71dfa8127bf8 (patch)
treed00c9059c9361920036e784425641288782515d5 /src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
parent1876e740a48be2e5ff5bd4fd6c2018927f1dcec2 (diff)
parentf26df23bbe0ae9b7162ed70369f24b01d75a1493 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala')
-rw-r--r--src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
index 2ef316bb..fa2c6f08 100644
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
@@ -80,4 +80,28 @@ class TruthTableSpec extends AnyFlatSpec {
}
assert(chisel3.stage.ChiselStage.emitChirrtl(new Foo) == chisel3.stage.ChiselStage.emitChirrtl(new Foo))
}
+ "TruthTable" should "accept unknown input width" in {
+ val t = TruthTable(
+ Seq(
+ BitPat(0.U) -> BitPat.dontCare(1),
+ BitPat(1.U) -> BitPat.dontCare(1),
+ BitPat(2.U) -> BitPat.dontCare(1),
+ BitPat(3.U) -> BitPat.dontCare(1),
+ BitPat(4.U) -> BitPat.dontCare(1),
+ BitPat(5.U) -> BitPat.dontCare(1),
+ BitPat(6.U) -> BitPat.dontCare(1),
+ BitPat(7.U) -> BitPat.dontCare(1)
+ ),
+ BitPat.N(1)
+ )
+ assert(t.toString contains "000->?")
+ assert(t.toString contains "001->?")
+ assert(t.toString contains "010->?")
+ assert(t.toString contains "011->?")
+ assert(t.toString contains "100->?")
+ assert(t.toString contains "101->?")
+ assert(t.toString contains "110->?")
+ assert(t.toString contains "111->?")
+ assert(t.toString contains " 0")
+ }
}