Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 4 insertions, 5 deletions

diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
index 255effaf..2ef316bb 100644
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
@@ -4,7 +4,7 @@ package chiselTests.util.experimental
 
 import chisel3._
 import chisel3.util.BitPat
-import chisel3.util.experimental.decode.{TruthTable, decoder}
+import chisel3.util.experimental.decode.{decoder, TruthTable}
 import org.scalatest.flatspec.AnyFlatSpec
 
 class TruthTableSpec extends AnyFlatSpec {
@@ -64,15 +64,14 @@ class TruthTableSpec extends AnyFlatSpec {
   "TruthTable" should "be reproducible" in {
     class Foo extends Module {
 
-      val io = IO(new Bundle{
+      val io = IO(new Bundle {
         val in = Input(UInt(4.W))
         val out = Output(UInt(16.W))
       })
 
-
       val table = TruthTable(
-        (0 until 16).map{
-          i => BitPat(i.U(4.W)) -> BitPat((1<<i).U(16.W))
+        (0 until 16).map { i =>
+          BitPat(i.U(4.W)) -> BitPat((1 << i).U(16.W))
         },
         BitPat.dontCare(16)
       )