Merge branch 'master' into 3.5-release

1 files changed, 42 insertions, 43 deletions

diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala
index 8120cc97..dd66ba40 100644
--- a/src/test/scala/chiselTests/util/BitSetSpec.scala
+++ b/src/test/scala/chiselTests/util/BitSetSpec.scala
@@ -6,14 +6,13 @@ import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
 class BitSetSpec extends AnyFlatSpec with Matchers {
-  behavior of classOf[BitSet].toString
+  behavior.of(classOf[BitSet].toString)
 
   it should "reject unequal width when constructing a BitSet" in {
     intercept[IllegalArgumentException] {
-      BitSet.fromString(
-        """b0010
-          |b00010
-          |""".stripMargin)
+      BitSet.fromString("""b0010
+                          |b00010
+                          |""".stripMargin)
     }
   }
 
@@ -21,7 +20,7 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
     val aBitPat = BitPat("b10?")
     val bBitPat = BitPat("b1??")
 
-    aBitPat.subtract(bBitPat).isEmpty should be (true)
+    aBitPat.subtract(bBitPat).isEmpty should be(true)
   }
 
   it should "return nonempty subtraction result correctly" in {
@@ -31,20 +30,19 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
     val dBitPat = BitPat("b100")
 
     val diffBitPat = bBitPat.subtract(aBitPat)
-    bBitPat.cover(diffBitPat) should be (true)
-    diffBitPat.equals(cBitPat) should be (true)
+    bBitPat.cover(diffBitPat) should be(true)
+    diffBitPat.equals(cBitPat) should be(true)
 
     val largerdiffBitPat = bBitPat.subtract(dBitPat)
-    aBitPat.cover(dBitPat) should be (true)
-    largerdiffBitPat.cover(diffBitPat) should be (true)
+    aBitPat.cover(dBitPat) should be(true)
+    largerdiffBitPat.cover(diffBitPat) should be(true)
   }
 
   it should "be able to handle complex subtract between BitSet" in {
-    val aBitSet = BitSet.fromString(
-      """b?01?0
-        |b11111
-        |b00000
-        |""".stripMargin)
+    val aBitSet = BitSet.fromString("""b?01?0
+                                      |b11111
+                                      |b00000
+                                      |""".stripMargin)
     val bBitSet = BitSet.fromString(
       """b?1111
         |b?0000
@@ -52,44 +50,41 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
     )
     val expected = BitPat("b?01?0")
 
-    expected.equals(aBitSet.subtract(bBitSet)) should be (true)
+    expected.equals(aBitSet.subtract(bBitSet)) should be(true)
   }
 
   it should "be generated from BitPat union" in {
-    val aBitSet = BitSet.fromString(
-      """b001?0
-        |b000??""".stripMargin)
+    val aBitSet = BitSet.fromString("""b001?0
+                                      |b000??""".stripMargin)
     val aBitPat = BitPat("b000??")
     val bBitPat = BitPat("b001?0")
     val cBitPat = BitPat("b00000")
-    aBitPat.cover(cBitPat) should be (true)
-    aBitSet.cover(bBitPat) should be (true)
+    aBitPat.cover(cBitPat) should be(true)
+    aBitSet.cover(bBitPat) should be(true)
 
-    aBitSet.equals(aBitPat.union(bBitPat)) should be (true)
+    aBitSet.equals(aBitPat.union(bBitPat)) should be(true)
   }
 
   it should "be generated from BitPat subtraction" in {
-    val aBitSet = BitSet.fromString(
-      """b001?0
-        |b000??""".stripMargin)
+    val aBitSet = BitSet.fromString("""b001?0
+                                      |b000??""".stripMargin)
     val aBitPat = BitPat("b00???")
     val bBitPat = BitPat("b001?1")
 
-    aBitSet.equals(aBitPat.subtract(bBitPat)) should be (true)
+    aBitSet.equals(aBitPat.subtract(bBitPat)) should be(true)
   }
 
   it should "union two BitSet together" in {
-    val aBitSet = BitSet.fromString(
-      """b001?0
-        |b001?1
-        |""".stripMargin)
+    val aBitSet = BitSet.fromString("""b001?0
+                                      |b001?1
+                                      |""".stripMargin)
     val bBitSet = BitSet.fromString(
       """b000??
         |b01???
         |""".stripMargin
     )
     val cBitPat = BitPat("b0????")
-    cBitPat.equals(aBitSet.union(bBitSet)) should be (true)
+    cBitPat.equals(aBitSet.union(bBitSet)) should be(true)
   }
 
   it should "be decoded" in {
@@ -100,19 +95,23 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
     chisel3.stage.ChiselStage.emitSystemVerilog(new Module {
       val in = IO(Input(UInt(8.W)))
       val out = IO(Output(UInt(4.W)))
-      out := decoder.bitset(in, Seq(
-        BitSet.fromString(
-          "b000?????"
+      out := decoder.bitset(
+        in,
+        Seq(
+          BitSet.fromString(
+            "b000?????"
+          ),
+          BitSet.fromString(
+            """b0010????
+              |b01??????
+              |""".stripMargin
+          ),
+          BitSet.fromString(
+            "b11??????"
+          )
         ),
-        BitSet.fromString(
-          """b0010????
-            |b01??????
-            |""".stripMargin
-        ),
-        BitSet.fromString(
-          "b11??????"
-        )
-      ), true)
+        true
+      )
     })
   }