diff options
| author | Jack | 2022-01-12 04:27:19 +0000 |
|---|---|---|
| committer | Jack | 2022-01-12 04:27:19 +0000 |
| commit | 29df513e348cc809876893f650af8180f0190496 (patch) | |
| tree | 06daaea954b4e5af7113f06e4bdbb78b33515cb3 /src/test/scala/chiselTests/util/BitPatSpec.scala | |
| parent | 5242ce90659decb9058ee75db56e5c188029fbf9 (diff) | |
| parent | 747d16311bdf185d2e98e452b14cb5d8ccca004c (diff) | |
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/util/BitPatSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/util/BitPatSpec.scala | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala index 549e8bca..38ffc3ba 100644 --- a/src/test/scala/chiselTests/util/BitPatSpec.scala +++ b/src/test/scala/chiselTests/util/BitPatSpec.scala @@ -6,13 +6,12 @@ import chisel3.util.BitPat import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers - class BitPatSpec extends AnyFlatSpec with Matchers { - behavior of classOf[BitPat].toString + behavior.of(classOf[BitPat].toString) it should "convert a BitPat to readable form" in { val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32 - BitPat("b" + testPattern).toString should be (s"BitPat($testPattern)") + BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)") } it should "convert a BitPat to raw form" in { @@ -21,15 +20,15 @@ class BitPatSpec extends AnyFlatSpec with Matchers { } it should "not fail if BitPat width is 0" in { - intercept[IllegalArgumentException]{BitPat("b")} + intercept[IllegalArgumentException] { BitPat("b") } } it should "concat BitPat via ##" in { - (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be (s"BitPat(1111???00)") + (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)") } it should "throw when BitPat apply to a Hardware" in { - intercept[java.lang.IllegalArgumentException]{ + intercept[java.lang.IllegalArgumentException] { chisel3.stage.ChiselStage.emitChirrtl(new chisel3.Module { BitPat(chisel3.Reg(chisel3.Bool())) }) |
