Merge pull request #1745 from chipsalliance/remove-val-io

Remove "val io" and rename MultiIOModule to Module

2 files changed, 40 insertions, 40 deletions

diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 5e7133d1..3a539bd4 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -11,7 +11,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   implicit val minimumScalaVersion: Int = 12
 
   "Scala plugin" should "name internally scoped components" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       { val mywire = Wire(UInt(3.W))}
     }
     aspectTest(() => new Test) {
@@ -20,8 +20,8 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Scala plugin" should "name internally scoped instances" in {
-    class Inner extends MultiIOModule { }
-    class Test extends MultiIOModule {
+    class Inner extends Module { }
+    class Test extends Module {
       { val myinstance = Module(new Inner) }
     }
     aspectTest(() => new Test) {
@@ -30,7 +30,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Scala plugin" should "interact with prefixing" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder() = {
         val wire = Wire(UInt(3.W))
       }
@@ -47,7 +47,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Scala plugin" should "interact with prefixing so last val name wins" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder() = {
         val wire1 = Wire(UInt(3.W))
         val wire2 = Wire(UInt(3.W))
@@ -71,7 +71,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Naming on option" should "work" in {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Option[UInt] = {
         val a = Wire(UInt(3.W))
         Some(a)
@@ -88,7 +88,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Naming on iterables" should "work" in {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Seq[UInt] = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -108,7 +108,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Naming on nested iterables" should "work" in {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Seq[Seq[UInt]] = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -137,7 +137,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   "Naming on custom case classes" should "not work" in {
     case class Container(a: UInt, b: UInt)
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): Container = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -167,7 +167,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Multiple names on a non-IO" should "get the first name" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val a = Wire(UInt(3.W))
         val b = a
@@ -234,7 +234,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
 
   "autoSeed" should "override automatic naming for non-IO" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val a = Wire(UInt(3.W))
         a.autoSeed("b")
@@ -248,7 +248,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Unapply assignments" should "still be named" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val (a, b) = (Wire(UInt(3.W)), Wire(UInt(3.W)))
       }
@@ -261,7 +261,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Unapply assignments" should "not override already named things" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val x = Wire(UInt(3.W))
         val (a, b) = (x, Wire(UInt(3.W)))
@@ -276,7 +276,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Case class unapply assignments" should "be named" in {
     case class Foo(x: UInt, y: UInt)
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         def func() = Foo(Wire(UInt(3.W)), Wire(UInt(3.W)))
         val Foo(a, b) = func()
@@ -291,7 +291,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
 
   "Complex unapply assignments" should "be named" in {
     case class Foo(x: UInt, y: UInt)
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val w = Wire(UInt(3.W))
         def func() = {
@@ -320,7 +320,7 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
   }
 
   "Nested val declarations" should "all be named" in {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val a = {
           val b = {
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index 83408dea..0712692d 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -10,7 +10,7 @@ import chiselTests.{ChiselPropSpec, Utils}
 class PrefixSpec extends ChiselPropSpec with Utils {
   implicit val minimumMajorVersion: Int = 12
   property("Scala plugin should interact with prefixing so last plugin name wins?") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val wire1 = Wire(UInt(3.W))
         val wire2 = Wire(UInt(3.W))
@@ -34,7 +34,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Nested prefixes should work") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder2(): UInt = {
         val wire1 = Wire(UInt(3.W))
         val wire2 = Wire(UInt(3.W))
@@ -68,7 +68,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing seeded with signal") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val wire = Wire(UInt(3.W))
         wire := 3.U
@@ -93,7 +93,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("Automatic prefixing should work") {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -113,7 +113,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("No prefixing annotation on defs should work") {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = noPrefix {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -130,7 +130,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("Prefixing on temps should work") {
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def builder(): UInt = {
         val a = Wire(UInt(3.W))
         val b = Wire(UInt(3.W))
@@ -149,13 +149,13 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should not leak into child modules") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       {
         val wire = Wire(UInt())
       }
     }
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val child = prefix("InTest") {
           Module(new Child)
@@ -169,13 +169,13 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should not leak into child modules, example 2") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       {
         val wire = Wire(UInt())
       }
     }
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       val x = IO(Input(UInt(3.W)))
       val y = {
         lazy val module = new Child
@@ -189,13 +189,13 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Instance names should not be added to prefix") {
-    class Child(tpe: UInt) extends MultiIOModule {
+    class Child(tpe: UInt) extends Module {
       {
         val io = IO(Input(tpe))
       }
     }
 
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         lazy val module = {
           val x = UInt(3.W)
@@ -212,7 +212,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
 
   property("Prefixing should not be caused by nested Iterable[Iterable[Any]]") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val iia = {
           val wire = Wire(UInt(3.W))
@@ -227,7 +227,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should be caused by nested Iterable[Iterable[Data]]") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val iia = {
           val wire = Wire(UInt(3.W))
@@ -242,7 +242,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing should be the prefix during the last call to autoName/suggestName") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val wire = {
           val x = Wire(UInt(3.W)).suggestName("mywire")
@@ -258,7 +258,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing have intuitive behavior") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val wire = {
           val x = Wire(UInt(3.W)).suggestName("mywire")
@@ -274,7 +274,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing on connection to subfields work") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val wire = Wire(new Bundle {
           val x = UInt(3.W)
@@ -301,12 +301,12 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing on connection to IOs should work") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       val in = IO(Input(UInt(3.W)))
       val out = IO(Output(UInt(3.W)))
       out := RegNext(in)
     }
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val child = Module(new Child)
         child.in := RegNext(3.U)
@@ -324,12 +324,12 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Prefixing on bulk connects should work") {
-    class Child extends MultiIOModule {
+    class Child extends Module {
       val in = IO(Input(UInt(3.W)))
       val out = IO(Output(UInt(3.W)))
       out := RegNext(in)
     }
-    class Test extends MultiIOModule {
+    class Test extends Module {
       {
         val child = Module(new Child)
         child.in <> RegNext(3.U)
@@ -347,7 +347,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Connections should use the non-prefixed name of the connected Data") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       prefix("foo") {
         val x = Wire(UInt(8.W))
         x := {
@@ -364,7 +364,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
   }
 
   property("Connections to aggregate fields should use the non-prefixed aggregate name") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       prefix("foo") {
         val x = Wire(new Bundle { val bar = UInt(8.W) })
         x.bar := {
@@ -382,7 +382,7 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
 
   property("Prefixing with wires in recursive functions should grow linearly") {
-    class Test extends MultiIOModule {
+    class Test extends Module {
       def func(bools: Seq[Bool]): Bool = {
         if (bools.isEmpty) true.B
         else {