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authorJack2022-07-30 22:41:15 +0000
committerJack2022-07-30 22:41:15 +0000
commit4cd44fa4dab370fcc5c20bcacc1fa0ee02327252 (patch)
tree05730be260feca0d2a870c4bb88325d36631a8fc /src/test/scala/chiselTests/naming/NamePluginSpec.scala
parentfe9635ef21bad233945617a24ab16cfa4055f2d1 (diff)
parentbced77045c8fc5db37e40b159c49220929e15d46 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/naming/NamePluginSpec.scala')
-rw-r--r--src/test/scala/chiselTests/naming/NamePluginSpec.scala38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 18359fd2..a787bb80 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -3,6 +3,7 @@
package chiselTests.naming
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.aop.Select
import chisel3.experimental.{prefix, treedump}
import chiselTests.{ChiselFlatSpec, Utils}
@@ -69,6 +70,24 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
}
}
+ "Scala plugin" should "name verification ops" in {
+ class Test extends Module {
+ val foo, bar = IO(Input(UInt(8.W)))
+
+ {
+ val x1 = chisel3.assert(1.U === 1.U)
+ val x2 = cover(foo =/= bar)
+ val x3 = chisel3.assume(foo =/= 123.U)
+ val x4 = printf("foo = %d\n", foo)
+ }
+ }
+ val chirrtl = ChiselStage.emitChirrtl(new Test)
+ (chirrtl should include).regex("assert.*: x1")
+ (chirrtl should include).regex("cover.*: x2")
+ (chirrtl should include).regex("assume.*: x3")
+ (chirrtl should include).regex("printf.*: x4")
+ }
+
"Naming on option" should "work" in {
class Test extends Module {
@@ -321,4 +340,23 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
Select.wires(top).map(_.instanceName) should be(List("a_b_c", "a_b", "a"))
}
}
+
+ behavior.of("Unnamed values (aka \"Temporaries\")")
+
+ they should "be declared by starting the name with '_'" in {
+ class Test extends Module {
+ {
+ val a = {
+ val b = {
+ val _c = Wire(UInt(3.W))
+ 4.U // literal so there is no name
+ }
+ b
+ }
+ }
+ }
+ aspectTest(() => new Test) { top: Test =>
+ Select.wires(top).map(_.instanceName) should be(List("_a_b_c"))
+ }
+ }
}