Merge pull request #1745 from chipsalliance/remove-val-io

Remove "val io" and rename MultiIOModule to Module

2 files changed, 8 insertions, 9 deletions

diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala
index d4ad4d67..b3534f11 100644
--- a/src/test/scala/chiselTests/experimental/ForceNames.scala
+++ b/src/test/scala/chiselTests/experimental/ForceNames.scala
@@ -14,7 +14,7 @@ import logger.{LogLevel, LogLevelAnnotation}
 
 /** Object containing Modules used for testing */
 object ForceNamesHierarchy {
-  class WrapperExample extends MultiIOModule {
+  class WrapperExample extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     val inst = Module(new Wrapper)
@@ -22,7 +22,7 @@ object ForceNamesHierarchy {
     out := inst.out
     forceName(out, "outt")
   }
-  class Wrapper extends MultiIOModule with InlineInstance {
+  class Wrapper extends Module with InlineInstance {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     val inst = Module(new MyLeaf)
@@ -30,12 +30,12 @@ object ForceNamesHierarchy {
     inst.in := in
     out := inst.out
   }
-  class MyLeaf extends MultiIOModule {
+  class MyLeaf extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     out := in
   }
-  class RenamePortsExample extends MultiIOModule {
+  class RenamePortsExample extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     val inst = Module(new MyLeaf)
@@ -43,13 +43,13 @@ object ForceNamesHierarchy {
     out := inst.out
     forceName(inst.in, "inn")
   }
-  class ConflictingName extends MultiIOModule {
+  class ConflictingName extends Module {
     val in = IO(Input(UInt(3.W)))
     val out = IO(Output(UInt(3.W)))
     out := in
     forceName(out, "in")
   }
-  class BundleName extends MultiIOModule {
+  class BundleName extends Module {
     val in = IO(new Bundle {
       val a = Input(UInt(3.W))
       val b = Input(UInt(3.W))
diff --git a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
index ffbdb814..ffe3a37f 100644
--- a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
+++ b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
@@ -52,12 +52,11 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
     doTest(new PortsWinTester)
   }
 
-  "LegacyModule" should "ignore suggestName on ports" in {
+  "Module" should "ignore suggestName on clock and reset" in {
     doTest(new Module with NamedModuleTester {
       val io = IO(new Bundle {
         val foo = Output(UInt(8.W))
       })
-      expectName(io.suggestName("cheese"), "io")
       expectName(clock.suggestName("tart"), "clock")
       expectName(reset.suggestName("teser"), "reset")
     })
@@ -65,7 +64,7 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
 
   "SuggestName collisions on ports" should "be illegal" in {
     a [ChiselException] should be thrownBy extractCause[ChiselException] {
-      ChiselStage.elaborate(new MultiIOModule {
+      ChiselStage.elaborate(new Module {
         val foo = IO(UInt(8.W)).suggestName("apple")
         val bar = IO(UInt(8.W)).suggestName("apple")
       })