Merge pull request #1481 from freechipsproject/driver-deprecations

Remove Deprecated Usages of chisel3.Driver, CircuitForm

2 files changed, 13 insertions, 15 deletions

diff --git a/src/test/scala/chiselTests/experimental/GroupSpec.scala b/src/test/scala/chiselTests/experimental/GroupSpec.scala
index 593179f4..f1820f5b 100644
--- a/src/test/scala/chiselTests/experimental/GroupSpec.scala
+++ b/src/test/scala/chiselTests/experimental/GroupSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.experimental
 import chiselTests.ChiselFlatSpec
 import chisel3._
 import chisel3.RawModule
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselMain}
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util.experimental.group
 import firrtl.analyses.InstanceGraph
 import firrtl.options.TargetDirAnnotation
@@ -31,15 +31,13 @@ class GroupSpec extends ChiselFlatSpec {
   }
 
   def lower[T <: RawModule](gen: () => T): fir.Circuit = {
-    (ChiselMain.stage.run(
-      Seq(
-        CompilerAnnotation(new LowFirrtlCompiler()),
-        TargetDirAnnotation("test_run_dir"),
-        ChiselGeneratorAnnotation(gen)
-      )
-    ) collectFirst {
-      case firrtl.stage.FirrtlCircuitAnnotation(circuit) => circuit
-    }).get
+    (new ChiselStage)
+      .execute(Array("--compiler", "low",
+                     "--target-dir", "test_run_dir"),
+               Seq(ChiselGeneratorAnnotation(gen)))
+      .collectFirst {
+        case firrtl.stage.FirrtlCircuitAnnotation(circuit) => circuit
+      }.get
   }
 
   "Module Grouping" should "compile to low FIRRTL" in {
diff --git a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
index 09e401f2..2cfc5f8d 100644
--- a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
+++ b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
@@ -4,6 +4,7 @@ package chiselTests
 package experimental
 
 import chisel3._
+import chisel3.stage.ChiselStage
 
 // NOTE This is currently an experimental API and subject to change
 // Example using a private port
@@ -31,11 +32,11 @@ class PortsWinTester extends NamedModuleTester {
   val output = expectName(IO(Output(UInt())).suggestName("wire"), "wire")
 }
 
-class ProgrammaticPortsSpec extends ChiselFlatSpec {
+class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
 
   private def doTest(testMod: => NamedModuleTester): Unit = {
     var module: NamedModuleTester = null
-    elaborate { module = testMod; module }
+    ChiselStage.elaborate { module = testMod; module }
     assert(module.getNameFailures() == Nil)
   }
 
@@ -63,12 +64,11 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec {
   }
 
   "SuggestName collisions on ports" should "be illegal" in {
-    a [ChiselException] should be thrownBy {
-      elaborate(new MultiIOModule {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate(new MultiIOModule {
         val foo = IO(UInt(8.W)).suggestName("apple")
         val bar = IO(UInt(8.W)).suggestName("apple")
       })
     }
   }
 }
-